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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id b8-20020adfe308000000b003436a3cae6dsm22982701wrj.98.2024.04.26.11.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 11:34:21 -0700 (PDT) From: Connor Abbott Date: Fri, 26 Apr 2024 19:34:04 +0100 Subject: [PATCH v2 6/6] drm/msm/a7xx: Add missing register writes from downstream Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240426-a750-raytracing-v2-6-562ac9866d63@gmail.com> References: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> In-Reply-To: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714156454; l=1002; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=egrZvhM+VJXYHLqq3OZ5q41AGIhcMaeNPTkRYlBKH78=; b=o9fdkDoS/YkfV/V0z0h6hIhKhzcieS6htACG9eESo5iKjrx59eF5rnL36c8VHWB1sjdqAe8SZ 0bXPLzO+8TPA2QIcjD1TetNUU4Znb1gyCaMCVQ6xIQbko3Za4x7ryPO X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= This isn't known to fix anything yet, but it's a good idea to add it. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 4a3b12b20802..d88ec857f1cb 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1953,6 +1953,14 @@ static int hw_init(struct msm_gpu *gpu) BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); } + if (adreno_is_a750(adreno_gpu)) { + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); + + gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); + } else if (adreno_is_a7xx(adreno_gpu)) { + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); + } + /* Enable interrupts */ gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK);