From patchwork Wed Apr 24 15:29:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xilin Wu via B4 Relay X-Patchwork-Id: 791626 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7AE61607A1; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; cv=none; b=maWpylZp96o6y7fXvt+Q9Et11/nBsysNf/QQsVGN5QnqfseVj4HKK4GsYlF0Npka4EHblr3z+SWWwL+bxzQeOZ2RLXswO2LauV/CMWNZDnO4Fw4o1s7JwrLS3kaJEvD4687CPjf3QJcIdh/Klh0MpWk+iTEJbch24hf8uhjuLuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713972571; c=relaxed/simple; bh=ps8qVqZjeKNfojZTva19k/8ll2iZtLvnZM7p9hTjE38=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=goAnt9R5DnYqc0Pl0gmxdMdgs51TmL+SoTaUS3yOBdyNBJbGr6PDXYyAHLoYWSQjrR1alz7pwDR2RkWZJWETHDd6n89z3PpnKpt5BhKNwMY2CmuEAQNQc4Bp7IYwOrGoUV9sN+bbdcF9GdemmDyKY2npg8HBjsoDgMO5CZUblgM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WWO/ztVX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WWO/ztVX" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7DED5C4AF49; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713972570; bh=ps8qVqZjeKNfojZTva19k/8ll2iZtLvnZM7p9hTjE38=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WWO/ztVXyClqShOKi1gpwGT2p+HM0JnU+aIW/o7CD9iTjQ5nLwHxknnGD9Apf9ki8 QTUIX1WWg9xWsknVmcZpt9hVcXBca4965XHycOD1pyaWwGVU7+qL9EMacLLE/iDntd QaHveJ7NveVPci8KaoslloczCJphpQrWOB9Bx+e4j8l9hzrN39U/i5Ij3YPyX6/Wkv CMd+wQk9ERJl81V3SzHhGy291jZn0+ibOFE1+SUzAHNPp2L0GUBmaF+nYXG2k+X+qT ibhtfN6hQ+UPfgkOxTuO0IbChSBTqcGpVv9Wf9c6v6tPHHpEGFa4RDAY/zoP4oEHvM 2Ppw5uMEEi0uw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72CDEC4345F; Wed, 24 Apr 2024 15:29:30 +0000 (UTC) From: Xilin Wu via B4 Relay Date: Wed, 24 Apr 2024 23:29:11 +0800 Subject: [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240424-ayn-odin2-initial-v1-6-e0aa05c991fd@gmail.com> References: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> In-Reply-To: <20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Junhao Xie , Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bjorn Andersson , Konrad Dybcio , Tengfei Fan , Molly Sophia , Junhao Xie Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Xilin Wu X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713972563; l=1572; i=wuxilin123@gmail.com; s=20240424; h=from:subject:message-id; bh=OFzbypiVPytW4zM7r7H6VNiMNFxsnAj0i8lBbxZUWk8=; b=tQq4dufCVktTutlbsclvej4fOdX/xDLlbF43Jmj8yh8O2UYPrLVmE/j5VMRLoF9xN9P9u7ToH 8xN5wY7sFBaCOU/0mIlgdQJD5X1zB0GGgNJcIwMJgMmy2rfyknDtryu X-Developer-Key: i=wuxilin123@gmail.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-Endpoint-Received: by B4 Relay for wuxilin123@gmail.com/20240424 with auth_id=157 X-Original-From: Xilin Wu Reply-To: wuxilin123@gmail.com From: Xilin Wu Add uart15 node for UART bus present on sm8550 SoC. Signed-off-by: Molly Sophia Signed-off-by: Xilin Wu Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index bc5aeb05ffc3..b8bbe88e770f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1122,6 +1122,20 @@ spi15: spi@89c000 { #size-cells = <0>; status = "disabled"; }; + + uart15: serial@89c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x89c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart15_default>; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; }; i2c_master_hub_0: geniqup@9c0000 { @@ -3856,6 +3870,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state { bias-pull-down; }; + qup_uart15_default: qup-uart15-default-state { + /* TX, RX */ + pins = "gpio74", "gpio75"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up; + }; + sdc2_sleep: sdc2-sleep-state { clk-pins { pins = "sdc2_clk";