From patchwork Thu Apr 18 09:23:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 789969 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE6D415B0E6; Thu, 18 Apr 2024 09:24:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713432279; cv=none; b=lGjajdRCxI3ShvqAnUfombuoZGDsm7oNlEBqU/nnqshc7vImZepb/x228qer0nE/8o1EgMePoKW5D2RLfQ2tbKgKf/qWOzTgzbMww0lvHRexrJAY3exg7Xd4SWhQbIcbNpzt0nIfrT6Niq3d3boGgFgpodS1prBzduZut0wkHf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713432279; c=relaxed/simple; bh=TI+Duxp2EJGVJ4LdDfnyodpBJpXYgGGAd/jITQiOpN0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=czn4y7/rJl/M0aeC2rmneQ2w/Xnh+UKCaifIt9oT/w8nrqluPEf3KAlYzGbqxBmDKX8fqmU7lkHWihwwrtk2w40hDII3xflwVXNQrTeji6FqyGTw7mryHimENE27E151tTcVpcDD/rxJrPDZjmgABXEOIuHMIWNzK85aF+nISbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ZPidlU95; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZPidlU95" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 43I6JibM007521; Thu, 18 Apr 2024 09:24:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=bTD3rZD1+ix+HL2KnDkU+hVfMXeUhq9jJbKM8O/mw78=; b=ZP idlU95whYITm5uDhrjfUteG63zAj5mwLtkWJk8BJiTi1PrpYaacLZAiwDioQsvwV Uu6M9qpXS5OtV9Q1R2JvuQIiHxB+nkmZ7uBcbSmG4IkyjKlLF9gzrHp0bs7cJqEi sIfPKbqixw5rfX2Re8b9JWUJPI8qTK6nLyjBtVkHMdpEI0wL1byxWq94ZTt306n3 InG/d/ZTPmJXM6odJdtE5YEJUHQQNBwIe99ttESbp2lX5ljC4oO2bBgrEUWNyE/0 ieVGTu40k7TsLA8ZbBt6+Mi7OIgmc523S8DE80z3heefLul5sa6HovSB5Q8l7CoC 5Loim04Q0qzZhDdpEugw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xjx54gdar-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Apr 2024 09:24:34 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43I9NslX012822 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Apr 2024 09:23:54 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 18 Apr 2024 02:23:49 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , Subject: [PATCH v9 4/6] clk: qcom: common: Add interconnect clocks support Date: Thu, 18 Apr 2024 14:53:03 +0530 Message-ID: <20240418092305.2337429-5-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418092305.2337429-1-quic_varada@quicinc.com> References: <20240418092305.2337429-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: j5yO9rlF3iYdUpt2CiCh0iVNw2cpMJ5G X-Proofpoint-ORIG-GUID: j5yO9rlF3iYdUpt2CiCh0iVNw2cpMJ5G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-18_08,2024-04-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404180066 Unlike MSM platforms that manage NoC related clocks and scaling from RPM, IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. However, there is a requirement to enable some NoC interface clocks for accessing the peripheral controllers present on these NoCs. Though exposing these as normal clocks would work, having a minimalistic interconnect driver to handle these clocks would make it consistent with other Qualcomm platforms resulting in common code paths. This is similar to msm8996-cbf's usage of icc-clk framework. Signed-off-by: Varadarajan Narayanan --- v9: Remove HWS_DATA macro v8: Explicitly set master and slave ids v7: Restore clk_get v6: first_id -> icc_first_node_id Remove clock get so that the peripheral that uses the clock can do the clock get v5: Split changes in common.c to separate patch Fix error handling Use devm_icc_clk_register instead of icc_clk_register v4: Use clk_hw instead of indices Do icc register in qcom_cc_probe() call stream Add icc clock info to qcom_cc_desc structure v3: Use indexed identifiers here to avoid confusion Fix error messages and move to common.c v2: Move DTS to separate patch Update commit log Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK to fix build error --- drivers/clk/qcom/common.c | 35 ++++++++++++++++++++++++++++++++++- drivers/clk/qcom/common.h | 9 +++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 75f09e6e057e..a6410b1828ca 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -234,6 +235,38 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; } +static int qcom_cc_icc_register(struct device *dev, + const struct qcom_cc_desc *desc) +{ + struct icc_clk_data *icd; + struct clk_hw *hws; + int i; + + if (!IS_ENABLED(CONFIG_INTERCONNECT_CLK)) + return 0; + + if (!desc->icc_hws) + return 0; + + icd = devm_kcalloc(dev, desc->num_icc_hws, sizeof(*icd), GFP_KERNEL); + if (!icd) + return -ENOMEM; + + for (i = 0; i < desc->num_icc_hws; i++) { + icd[i].master_id = desc->icc_hws[i].master_id; + icd[i].slave_id = desc->icc_hws[i].slave_id; + hws = &desc->clks[desc->icc_hws[i].clk_id]->hw; + icd[i].clk = devm_clk_hw_get_clk(dev, hws, "icc"); + if (!icd[i].clk) + return dev_err_probe(dev, -ENOENT, + "(%d) clock entry is null\n", i); + icd[i].name = clk_hw_get_name(hws); + } + + return devm_icc_clk_register(dev, desc->icc_first_node_id, + desc->num_icc_hws, icd); +} + int qcom_cc_really_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc, struct regmap *regmap) { @@ -303,7 +336,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, if (ret) return ret; - return 0; + return qcom_cc_icc_register(dev, desc); } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 9c8f7b798d9f..ea96b2ca3cac 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -19,6 +19,12 @@ struct clk_hw; #define PLL_VOTE_FSM_ENA BIT(20) #define PLL_VOTE_FSM_RESET BIT(21) +struct qcom_icc_hws_data { + int master_id; + int slave_id; + int clk_id; +}; + struct qcom_cc_desc { const struct regmap_config *config; struct clk_regmap **clks; @@ -29,6 +35,9 @@ struct qcom_cc_desc { size_t num_gdscs; struct clk_hw **clk_hws; size_t num_clk_hws; + struct qcom_icc_hws_data *icc_hws; + size_t num_icc_hws; + unsigned int icc_first_node_id; }; /**