From patchwork Fri Apr 12 12:36:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fenglin Wu via B4 Relay X-Patchwork-Id: 788600 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CA5250A68; Fri, 12 Apr 2024 12:36:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712925406; cv=none; b=TMs/6vRbwnl6hiRjoakp0dwHUZvfpd6uCDDozB1kbbko55X2QKTdOByHhHC65LrjYQ9fJ7Gh/L7cFQC6tF1djnqD4p7tiEnBQtzOL0zctJjJTBvIUoLLpIgAlnddNjNMgb4w4ZlJjUYyK62qnKM9NQ8kMz1ryMd9KbvnrVE3wQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712925406; c=relaxed/simple; bh=yHrtARBaJjouW6QVoijuifz4Jy/hgSa1MM7EatAgWSc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FOUIKXd6rFy8gssgdAOCedvEz/hLLhTn4ntTN+PNfcKaND9X/AuW7bReRAgn6nCoONuEOQ3pk9BEDxU900q9oy/itsNv0V5WmSG5oT0mTNAeXsHwdbFr6ZSDIXFT5lrS8Jw4SmZfERceDXGefT0rDVYKFQzSrkfvUo+/6TGP3QI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P9tHaJxA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P9tHaJxA" Received: by smtp.kernel.org (Postfix) with ESMTPS id 38095C2BD10; Fri, 12 Apr 2024 12:36:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712925406; bh=yHrtARBaJjouW6QVoijuifz4Jy/hgSa1MM7EatAgWSc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=P9tHaJxAdU9lS1D4u9QRjKSogr+UY1RvYnad3ymrUM44lrEzBMTuUcWsW2dCXtizl ghj0C9ByV154qjPQXseRMt/nLPpi3PedPhy1Eh083C4/oN08YBNvv2ksap3XX7e8XR 2AGuFUA3HhXp3PqSZ/OqC8kf5sX127+VmYIkyg4TuDuCpKj9AOwGzxR7r7aYZcD3er KBghrVhXK9muqkAQqyhCXdRBlP8pN4Ox2LHNW5gzt1gZiZHGR10SRkYMfAWNgjbjVn Xxzr3uYBi+5mAPUAqBd5EWsfoAX20mDZTy4Obz0qkKr+Nh7j+Uazip+t+KY2PAB3gg UTqb/yhrs5q7w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2400EC41513; Fri, 12 Apr 2024 12:36:46 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Fri, 12 Apr 2024 20:36:26 +0800 Subject: [PATCH v10 2/4] input: pm8xxx-vibrator: refactor to support new SPMI vibrator Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240412-pm8xxx-vibrator-new-design-v10-2-0ec0ad133866@quicinc.com> References: <20240412-pm8xxx-vibrator-new-design-v10-0-0ec0ad133866@quicinc.com> In-Reply-To: <20240412-pm8xxx-vibrator-new-design-v10-0-0ec0ad133866@quicinc.com> To: kernel@quicinc.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-input@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Fenglin Wu X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1712925404; l=4328; i=quic_fenglinw@quicinc.com; s=20240327; h=from:subject:message-id; bh=Z23TYMEBk9Q8HS6GaIPC6RDcCQ+axWSc4H0ISoYYLRc=; b=+vDlS5D319hE8n7YqmWl6RfFPnd9GqnpdIasC0UIGUkQBurWArorTBCrs/q84JYlsO87Wse0F ZrLKJRXqSVwD6hm6KaB5AMroB/uEgBRUSj+CDHJDHUlt+90Jfk57NWD X-Developer-Key: i=quic_fenglinw@quicinc.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for quic_fenglinw@quicinc.com/20240327 with auth_id=146 X-Original-From: Fenglin Wu Reply-To: quic_fenglinw@quicinc.com From: Fenglin Wu Currently, vibrator control register addresses are hard coded, including the base address and offsets, it's not flexible to support new SPMI vibrator module which is usually included in different PMICs with different base address. Refactor it by using the base address defined in devicetree. Signed-off-by: Fenglin Wu --- drivers/input/misc/pm8xxx-vibrator.c | 41 +++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/input/misc/pm8xxx-vibrator.c b/drivers/input/misc/pm8xxx-vibrator.c index 844ca7e1f59f..640927f94143 100644 --- a/drivers/input/misc/pm8xxx-vibrator.c +++ b/drivers/input/misc/pm8xxx-vibrator.c @@ -20,27 +20,27 @@ #define MAX_FF_SPEED 0xff struct pm8xxx_regs { - unsigned int enable_addr; + unsigned int enable_offset; unsigned int enable_mask; - unsigned int drv_addr; + unsigned int drv_offset; unsigned int drv_mask; unsigned int drv_shift; unsigned int drv_en_manual_mask; }; static const struct pm8xxx_regs pm8058_regs = { - .drv_addr = 0x4A, + .drv_offset = 0, .drv_mask = 0xf8, .drv_shift = 3, .drv_en_manual_mask = 0xfc, }; static struct pm8xxx_regs pm8916_regs = { - .enable_addr = 0xc046, + .enable_offset = 0x46, .enable_mask = BIT(7), - .drv_addr = 0xc041, - .drv_mask = 0x1F, + .drv_offset = 0x41, + .drv_mask = 0x1f, .drv_shift = 0, .drv_en_manual_mask = 0, }; @@ -51,6 +51,8 @@ static struct pm8xxx_regs pm8916_regs = { * @work: work structure to set the vibration parameters * @regmap: regmap for register read/write * @regs: registers' info + * @enable_addr: vibrator enable register + * @drv_addr: vibrator drive strength register * @speed: speed of vibration set from userland * @active: state of vibrator * @level: level of vibration to set in the chip @@ -61,6 +63,8 @@ struct pm8xxx_vib { struct work_struct work; struct regmap *regmap; const struct pm8xxx_regs *regs; + unsigned int enable_addr; + unsigned int drv_addr; int speed; int level; bool active; @@ -83,15 +87,15 @@ static int pm8xxx_vib_set(struct pm8xxx_vib *vib, bool on) else val &= ~regs->drv_mask; - rc = regmap_write(vib->regmap, regs->drv_addr, val); + rc = regmap_write(vib->regmap, vib->drv_addr, val); if (rc < 0) return rc; vib->reg_vib_drv = val; if (regs->enable_mask) - rc = regmap_update_bits(vib->regmap, regs->enable_addr, - regs->enable_mask, on ? ~0 : 0); + rc = regmap_update_bits(vib->regmap, vib->enable_addr, + regs->enable_mask, on ? regs->enable_mask : 0); return rc; } @@ -103,11 +107,10 @@ static int pm8xxx_vib_set(struct pm8xxx_vib *vib, bool on) static void pm8xxx_work_handler(struct work_struct *work) { struct pm8xxx_vib *vib = container_of(work, struct pm8xxx_vib, work); - const struct pm8xxx_regs *regs = vib->regs; - int rc; unsigned int val; + int rc; - rc = regmap_read(vib->regmap, regs->drv_addr, &val); + rc = regmap_read(vib->regmap, vib->drv_addr, &val); if (rc < 0) return; @@ -170,7 +173,7 @@ static int pm8xxx_vib_probe(struct platform_device *pdev) struct pm8xxx_vib *vib; struct input_dev *input_dev; int error; - unsigned int val; + unsigned int val, reg_base = 0; const struct pm8xxx_regs *regs; vib = devm_kzalloc(&pdev->dev, sizeof(*vib), GFP_KERNEL); @@ -188,15 +191,23 @@ static int pm8xxx_vib_probe(struct platform_device *pdev) INIT_WORK(&vib->work, pm8xxx_work_handler); vib->vib_input_dev = input_dev; + error = fwnode_property_read_u32(pdev->dev.fwnode, "reg", ®_base); + if (error < 0) { + dev_err(&pdev->dev, "Failed to read reg address, rc=%d\n", error); + return error; + } + regs = of_device_get_match_data(&pdev->dev); + vib->enable_addr = reg_base + regs->enable_offset; + vib->drv_addr = reg_base + regs->drv_offset; /* operate in manual mode */ - error = regmap_read(vib->regmap, regs->drv_addr, &val); + error = regmap_read(vib->regmap, vib->drv_addr, &val); if (error < 0) return error; val &= regs->drv_en_manual_mask; - error = regmap_write(vib->regmap, regs->drv_addr, val); + error = regmap_write(vib->regmap, vib->drv_addr, val); if (error < 0) return error;