| Message ID | 20240408-dispcc-dp-clocks-v1-3-f9e44902c28d@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: dispcc: fix DisplayPort link clocks | expand |
On 08/04/2024 13:47, Dmitry Baryshkov wrote: > On SM8550 DisplayPort link clocks use frequency tables inherited from > the vendor kernel, it is not applicable in the upstream kernel. Drop > frequency tables and use clk_byte2_ops for those clocks. > > Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/dispcc-sm8550.c | 20 ++++---------------- > 1 file changed, 4 insertions(+), 16 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c > index 3672c73ac11c..38ecea805503 100644 > --- a/drivers/clk/qcom/dispcc-sm8550.c > +++ b/drivers/clk/qcom/dispcc-sm8550.c > @@ -345,26 +345,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { > }, > }; > > -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { > - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - { } > -}; > - > static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { > .cmd_rcgr = 0x8170, > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_7, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_link_clk_src", > .parent_data = disp_cc_parent_data_7, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > @@ -418,13 +409,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > @@ -478,13 +468,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > @@ -538,13 +527,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Fixes the: [ 25.428008] msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22 Thanks ! Neil
diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 3672c73ac11c..38ecea805503 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -345,26 +345,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { }, }; -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { .cmd_rcgr = 0x8170, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_7, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_clk_src", .parent_data = disp_cc_parent_data_7, .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -418,13 +409,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -478,13 +468,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -538,13 +527,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, };
On SM8550 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sm8550.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-)