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Mon, 01 Apr 2024 13:33:44 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j11-20020ac2550b000000b00515a6e4bdbdsm1478342lfk.250.2024.04.01.13.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Apr 2024 13:33:44 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 01 Apr 2024 23:33:42 +0300 Subject: [PATCH v3 3/9] arm64: dts: qcom: sm8250: describe HS signals properly Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240401-typec-fix-sm8250-v3-3-604dce3ad103@linaro.org> References: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2725; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=CLQVhmk/27P67Q5DDFf+FMW5mOTK698dPfd2w+evFJI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmCxolBUPQlAYOIefb8KyuYOLAtq6877RLYQh43 QZgXF2CyuOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZgsaJQAKCRCLPIo+Aiko 1Wf8B/9Pm78kXmduvIoq5pA27/BiuNgtFW3USGWltyqAMieojp1D5zEE67t/h5A/x1LHwOUyzdd g1AkILqZT2wUyg2ZY6JhuZE+voEGEkhYV9bULkhkiT4Egcx0ybtDyoI3OV3uRWoRzpy0jLHdx/0 5Nm7QTtE8dKEKDPqJ6EQ0Zv61j1Vd51JgtmJU4pHcXTXmQ4am3WU6+G7Dt+RE9BzeFKUQOcOWP5 Xt4oWGQeUuoFmzWfBTMnFMwyYXgyxvv+kaAL6ZrZ+8T11P7Hwoxk5frc5WW5xNgU5tqGTQvoEAW VKGboz6AcVlWLj+SitfgrC1biUXfHGGmp9TOl1HviMK+ZV9X X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The OF graph should describe physical signals. There is no 'role switch' signal between Type-C connector and the DWC3 USB controller. Instead there is a HighSpeed signal lane between DWC3 controller and the USB-C connector. Rename endpoints in accordance to that (this follows the example lead by other plaforms, including QRB2210 RB1, QRB4210 RB2 and all PMIC GLINK platforms). Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index cd0db4f31d4a..44239d1e57e9 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1356,8 +1356,8 @@ &usb_1_dwc3 { usb-role-switch; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &usb_1_hsphy { @@ -1465,8 +1465,8 @@ ports { port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 2042020eb0dd..6cc0bcb40f1f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -659,8 +659,8 @@ ports { port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; }; @@ -723,8 +723,8 @@ &usb_1_hsphy { status = "okay"; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7f2333c9d17d..440bbb89bf8a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4196,7 +4196,7 @@ usb_1_dwc3: usb@a600000 { phy-names = "usb2-phy", "usb3-phy"; port { - usb_1_role_switch_out: endpoint {}; + usb_1_dwc3_hs_out: endpoint {}; }; }; };