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Mon, 01 Apr 2024 13:33:43 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j11-20020ac2550b000000b00515a6e4bdbdsm1478342lfk.250.2024.04.01.13.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Apr 2024 13:33:43 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 01 Apr 2024 23:33:40 +0300 Subject: [PATCH v3 1/9] dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240401-typec-fix-sm8250-v3-1-604dce3ad103@linaro.org> References: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2305; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Pl/YNaCowSJwtvM5CLxzriI2N0LVr+hVT798TnH3gks=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQxq3lIqm7YesxMjpRxoP5kv2/Ug6lRzhmWB9y8BpTpPax PZkb81ORmMWBkYuBlkxRRafgpapMZuSwz7smFoPM4iVCWQKAxenAExk+1kOhokG7wu+yt4UyJ59 4E/w7Q8fEmbbFn6cHhv2ui3+1pnAz4HeHOalXCt2mao3Wz/8dGbfbWuL8CjldneFWb9U3+Q/FX6 g9/WNysfIlPUvowRy8jyuZb+w+mLrIrfaoWD7h9jeSzfV3Y/8WiJYOEXC457qfk4bxT3HY3jdmy +K3hfnjJvz8UtppVz8n028KskRu/65L/xTbabI/dLI93IB75uH7y09JpRMVQpu0visnFuwVprrU UFko68i9yoxozMPNi843iCa3yVtpZL2+oGRDMf7wG9X2Bj8/ENFMm5IRf7/6KlyP7/BedF+ltLe W8UbX+6WFT9baTTz7fvGy+tNl+/6mscq9l2c+doZ1XnXAQ== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On the affected Qualcomm platforms the display clock controller has additional DP input clocks, describe them in DT schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 59cc88a52f6b..5831579b572e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -27,6 +27,7 @@ properties: - qcom,sm8350-dispcc clocks: + minItems: 7 items: - description: Board XO source - description: Byte clock from DSI PHY0 @@ -35,8 +36,15 @@ properties: - description: Pixel clock from DSI PHY1 - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY + - description: Link clock from eDP PHY + - description: VCO DIV clock from eDP PHY + - description: Link clock from DP1 PHY + - description: VCO DIV clock from DP1 PHY + - description: Link clock from DP2 PHY + - description: VCO DIV clock from DP2 PHY clock-names: + minItems: 7 items: - const: bi_tcxo - const: dsi0_phy_pll_out_byteclk @@ -45,6 +53,12 @@ properties: - const: dsi1_phy_pll_out_dsiclk - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk + - const: edp_phy_pll_link_clk + - const: edp_phy_pll_vco_div_clk + - const: dptx1_phy_pll_link_clk + - const: dptx1_phy_pll_vco_div_clk + - const: dptx2_phy_pll_link_clk + - const: dptx2_phy_pll_vco_div_clk '#clock-cells': const: 1 @@ -68,6 +82,20 @@ properties: A phandle to an OPP node describing required MMCX performance point. maxItems: 1 +allOf: + - if: + not: + properties: + compatible: + contains: + const: qcom,sc8180x-dispcc + then: + properties: + clocks: + maxItems: 7 + clock-names: + maxItems: 7 + required: - compatible - reg