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Wed, 27 Mar 2024 02:04:31 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 26 Mar 2024 19:04:31 -0700 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:23 -0700 Subject: [PATCH v2 6/6] arm64: defconfig: Enable sc7280 display and gpu clock controllers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240326-rb3gen2-dp-connector-v2-6-a9f1bc32ecaf@quicinc.com> References: <20240326-rb3gen2-dp-connector-v2-0-a9f1bc32ecaf@quicinc.com> In-Reply-To: <20240326-rb3gen2-dp-connector-v2-0-a9f1bc32ecaf@quicinc.com> To: , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Dmitry Baryshkov CC: , , , , "Bjorn Andersson" X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1711505069; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6c45a465a071..a25a28e6117b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1287,6 +1287,7 @@ CONFIG_QCM_DISPCC_2290=m CONFIG_QCS_GCC_404=y CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m +CONFIG_SC_DISPCC_7280=m CONFIG_SC_DISPCC_8280XP=m CONFIG_SA_GCC_8775P=y CONFIG_SA_GPUCC_8775P=m @@ -1294,6 +1295,7 @@ CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y CONFIG_SC_GCC_8180X=y CONFIG_SC_GCC_8280XP=y +CONFIG_SC_GPUCC_7280=m CONFIG_SC_GPUCC_8280XP=m CONFIG_SC_LPASSCC_8280XP=m CONFIG_SDM_CAMCC_845=m