@@ -22,9 +22,7 @@ struct dp_audio_private {
struct platform_device *pdev;
struct drm_device *drm_dev;
struct dp_catalog *catalog;
- struct dp_panel *panel;
- bool engine_on;
u32 channels;
struct dp_audio dp_audio;
@@ -356,8 +354,6 @@ static void dp_audio_enable(struct dp_audio_private *audio, bool enable)
catalog->audio_data = enable;
dp_catalog_audio_enable(catalog);
-
- audio->engine_on = enable;
}
static struct dp_audio_private *dp_audio_get_data(struct platform_device *pdev)
@@ -571,7 +567,6 @@ struct dp_audio *dp_audio_get(struct platform_device *pdev,
}
audio->pdev = pdev;
- audio->panel = panel;
audio->catalog = catalog;
dp_audio = &audio->dp_audio;
@@ -81,7 +81,6 @@ struct dp_catalog_private {
struct dss_io_data io;
u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
struct dp_catalog dp_catalog;
- u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX];
};
void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state)
@@ -28,26 +28,9 @@
#define DP_INTR_FRAME_END BIT(6)
#define DP_INTR_CRC_UPDATED BIT(9)
-#define DP_AUX_CFG_MAX_VALUE_CNT 3
-
#define DP_HW_VERSION_1_0 0x10000000
#define DP_HW_VERSION_1_2 0x10020000
-/* PHY AUX config registers */
-enum dp_phy_aux_config_type {
- PHY_AUX_CFG0,
- PHY_AUX_CFG1,
- PHY_AUX_CFG2,
- PHY_AUX_CFG3,
- PHY_AUX_CFG4,
- PHY_AUX_CFG5,
- PHY_AUX_CFG6,
- PHY_AUX_CFG7,
- PHY_AUX_CFG8,
- PHY_AUX_CFG9,
- PHY_AUX_CFG_MAX,
-};
-
enum dp_catalog_audio_sdp_type {
DP_AUDIO_SDP_STREAM,
DP_AUDIO_SDP_TIMESTAMP,
@@ -12,7 +12,6 @@
#include "dp_catalog.h"
struct dp_ctrl {
- atomic_t aborted;
bool wide_bus_en;
};
@@ -74,7 +74,6 @@ struct dp_event {
};
struct dp_display_private {
- char *name;
int irq;
unsigned int id;
@@ -82,11 +81,9 @@ struct dp_display_private {
/* state variables */
bool core_initialized;
bool phy_initialized;
- bool hpd_irq_on;
bool audio_supported;
struct drm_device *drm_dev;
- struct dentry *root;
struct dp_catalog *catalog;
struct drm_dp_aux *aux;
@@ -800,7 +797,6 @@ static int dp_display_set_mode(struct msm_dp *dp_display,
drm_mode_copy(&dp->panel->dp_mode.drm_mode, &mode->drm_mode);
dp->panel->dp_mode.bpp = mode->bpp;
- dp->panel->dp_mode.capabilities = mode->capabilities;
dp->panel->dp_mode.out_fmt_is_yuv_420 = mode->out_fmt_is_yuv_420;
dp_panel_init_panel_info(dp->panel);
return 0;
@@ -1260,7 +1256,6 @@ static int dp_display_probe(struct platform_device *pdev)
return -EINVAL;
dp->dp_display.pdev = pdev;
- dp->name = "drm_dp";
dp->id = desc->id;
dp->dp_display.connector_type = desc->connector_type;
dp->wide_bus_supported = desc->wide_bus_supported;
@@ -16,7 +16,6 @@ struct msm_dp {
struct drm_device *drm_dev;
struct platform_device *pdev;
struct device *codec_dev;
- struct drm_bridge *bridge;
struct drm_connector *connector;
struct drm_bridge *next_bridge;
bool link_ready;
@@ -28,8 +27,6 @@ struct msm_dp {
hdmi_codec_plugged_cb plugged_cb;
- bool wide_bus_en;
-
struct dp_audio *dp_audio;
bool psr_supported;
};
@@ -347,8 +347,6 @@ int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
}
}
- dp_display->bridge = bridge;
-
return 0;
}
@@ -36,7 +36,6 @@ struct dp_link_request {
struct dp_link_private {
u32 prev_sink_count;
- struct device *dev;
struct drm_device *drm_dev;
struct drm_dp_aux *aux;
struct dp_link dp_link;
@@ -804,8 +803,6 @@ int dp_link_psm_config(struct dp_link *dp_link,
if (ret)
DRM_ERROR("Failed to %s low power mode\n", enable ?
"enter" : "exit");
- else
- dp_link->psm_enabled = enable;
mutex_unlock(&link->psm_mutex);
return ret;
@@ -1226,7 +1223,6 @@ struct dp_link *dp_link_get(struct device *dev, struct drm_dp_aux *aux)
if (!link)
return ERR_PTR(-ENOMEM);
- link->dev = dev;
link->aux = aux;
mutex_init(&link->psm_mutex);
@@ -74,7 +74,6 @@ struct dp_link_phy_params {
struct dp_link {
u32 sink_request;
u32 test_response;
- bool psm_enabled;
u8 sink_count;
struct dp_link_test_video test_video;
@@ -15,7 +15,6 @@ struct edid;
struct dp_display_mode {
struct drm_display_mode drm_mode;
- u32 capabilities;
u32 bpp;
u32 h_active_low;
u32 v_active_low;
@@ -47,7 +46,6 @@ struct dp_panel {
bool video_test;
bool vsc_sdp_supported;
- u32 vic;
u32 max_dp_lanes;
u32 max_dp_link_rate;