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Thu, 21 Mar 2024 04:17:53 -0700 (PDT) Received: from [127.0.1.1] ([2409:40f4:102b:a64b:d832:a82a:837c:6d3]) by smtp.gmail.com with ESMTPSA id ka6-20020a056a00938600b006e7324d32bbsm5531120pfb.122.2024.03.21.04.17.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 04:17:53 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:38 +0530 Subject: [PATCH v2 18/21] ARM: dts: qcom: ipq4019: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-pcie-qcom-bridge-dts-v2-18-1eb790c53e43@linaro.org> References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 681cb3fc8085..f09c123d9fa2 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -470,6 +470,16 @@ pcie0: pcie@40000000 { "phy_ahb"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; qpic_bam: dma-controller@7984000 {