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Thu, 21 Mar 2024 04:17:41 -0700 (PDT) Received: from [127.0.1.1] ([2409:40f4:102b:a64b:d832:a82a:837c:6d3]) by smtp.gmail.com with ESMTPSA id ka6-20020a056a00938600b006e7324d32bbsm5531120pfb.122.2024.03.21.04.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 04:17:40 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:35 +0530 Subject: [PATCH v2 15/21] arm64: dts: qcom: ipq8074: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-pcie-qcom-bridge-dts-v2-15-1eb790c53e43@linaro.org> References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1264; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=c14pcQ7llIjx8mdlZCcx/UxdVlyVw3faEieM5GK4g1Y=; b=owGbwMvMwMUYOl/w2b+J574ynlZLYkj9I87juUeyJOlTUEpJ2ZUqi9jl6rdWZWyP8V9kE63Px Skob3ipk9GYhYGRi0FWTJElfamzVqPH6RtLItSnwwxiZQKZwsDFKQATObeL/TdrT9jLAs9LQkU8 GruFdRf9+5VT2W386Vrd3XO7XX/Ke8zrvsAdcmZLimi87sS5DGf+eU/bUJ7XwlanurrN+WCahZ2 eZx6PZdyak2+v/hdav9NSIPj47crN7Bt7eizvp2SE1zYsk5n7r+d08OtXWV+u5SvMMmwU0Vq/Zk mcWWmD++2MLPbk37dMZI7O2ioq6vajSDovTZol0U/bIe/m3eRV3yqDXRqD7X6nbcmZ0PlK8ZlQw DcL7iKxKZs9js068fMG/8nZbJrBlT80trZnZx2fLrqJO+y90aIVAW7V5+OnNr9Q9sty/Os7R1yB reOp7o3IaU5HU72dVXseHP9RUOYYXx76I3/xdY0LHIt6AQ== X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index e5b89753aa5c..12324841d1b0 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -864,6 +864,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "ahb", "axi_m_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0: pcie@20000000 { @@ -929,6 +939,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_m_sticky", "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; };