| Message ID | 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-5-926d7a4ccd80@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs | expand |
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b86be34a912b..32361af98936 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,8 +754,8 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <0>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -1988,8 +1988,8 @@ pcie1_phy: phy@1c0e000 { "rchng", "pipe"; - clock-output-names = "pcie_1_pipe_clk"; - #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk"; + #clock-cells = <1>; #phy-cells = <0>;
Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy provided QMP_PCIE_PHY_AUX_CLK. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)