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Tue, 05 Mar 2024 02:54:10 +0000 Received: from NALASPPMTA05.qualcomm.com (NALASPPMTA05.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4252sAos013875; Tue, 5 Mar 2024 02:54:10 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-qianyu-lv.qualcomm.com [10.81.25.114]) by NALASPPMTA05.qualcomm.com (PPS) with ESMTPS id 4252sAGc013874 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 05 Mar 2024 02:54:10 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4098150) id 4E6975CA; Mon, 4 Mar 2024 18:54:10 -0800 (PST) From: Qiang Yu To: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_cang@quicinc.com, quic_mrana@quicinc.com, quic_qianyu@quicinc.com Subject: [PATCH v3] arm64: dts: qcom: sm8550: Increase supported MSI interrupts Date: Mon, 4 Mar 2024 18:54:08 -0800 Message-Id: <20240305025408.3380561-1-qianyu@qti.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UGIzq7y562vGyiiy7KTruY7yUMqAi6e8 X-Proofpoint-ORIG-GUID: UGIzq7y562vGyiiy7KTruY7yUMqAi6e8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-04_20,2024-03-04_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 clxscore=1011 lowpriorityscore=0 adultscore=1 malwarescore=0 priorityscore=1501 bulkscore=0 impostorscore=0 mlxlogscore=553 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403050020 From: Qiang Yu On sm8550, synopsys MSI controller supports 256 MSI interrupts. Hence, enable all GIC interrupts required by MSI controller for PCIe0 and PCIe1. Signed-off-by: Qiang Yu Reviewed-by: Konrad Dybcio --- v1->v2: make interrupt-names one per line v2->v3: delete dot in the end of subject arch/arm64/boot/dts/qcom/sm8550.dtsi | 36 ++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..3f413cba2428 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1713,8 +1713,22 @@ pcie0: pcie@1c00000 { linux,pci-domain = <0>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1804,8 +1818,22 @@ pcie1: pcie@1c08000 { linux,pci-domain = <1>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>;