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Tue, 20 Feb 2024 19:42:10 -0800 (PST) Received: from [127.0.1.1] ([117.207.28.224]) by smtp.gmail.com with ESMTPSA id o23-20020a056a001b5700b006e466369645sm4436231pfv.132.2024.02.20.19.42.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 19:42:10 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 21 Feb 2024 09:11:47 +0530 Subject: [PATCH 01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240221-pcie-qcom-bridge-dts-v1-1-6c6df0f9450d@linaro.org> References: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> In-Reply-To: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1536; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=uG/9KOG8Z17eKXEtbxH9o5AmhzmNnY1T/Q7m5dFGLnw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl1XEF9/fHNekkvPUiaqVD1hZQ8DqFjrazu7GqQ IHE7EVUO76JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZdVxBQAKCRBVnxHm/pHO 9aefB/wOjD+6DG3lTAmXaj2NFcWPHTZlUrH+fNNDnmDiSjCYy1JhJV1mRvt6uqqoAvEjKOs5jAL XU69S7rZ/WPztMNu/HWFJBXdaPFpBfVqgU7isZCbtV/rsziS+4zPpnIlQ5qDN4kiUFJBNiMVYxE muUtwqZbCn5mk93f7nwDi17H1p4CvgVOmHw8lT0kgEWUtOmVBAW8lLFutR7PzEKL1/u/wtWBATr RnRYQ8SG9qPb+CWgVyagKenq16lkhab1jMvW7ACR9wXTtggQToeexOIDpN/7/ufZ7VNL1AdcY75 MMmWI01hqDfvEgm+hzw/lVUxWUuhMAG+jNEmU2nz9hYMqfoV X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 760501c1301a..0c61623d9be9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2197,6 +2197,16 @@ pcie0: pcie@1c00000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2298,6 +2308,16 @@ pcie1: pcie@1c08000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -2399,6 +2419,16 @@ pcie2: pcie@1c10000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2_phy: phy@1c16000 {