diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-camcc.yaml
new file mode 100644
index 000000000000..7be4b10c430c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-camcc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller on SM7150
+
+maintainers:
+  - Danila Tikhonov <danila@jiaxyga.com>
+  - David Wronek <david@mainlining.org>
+  - Jens Reidel <adrian@travitia.xyz>
+
+description: |
+  Qualcomm camera clock control module provides the clocks, resets and power
+  domains on SM7150.
+
+  See also:: include/dt-bindings/clock/qcom,sm7150-camcc.h
+
+properties:
+  compatible:
+    const: qcom,sm7150-camcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board XO Active-Only source
+      - description: Sleep clock source
+
+  power-domains:
+    maxItems: 1
+    description:
+      CX power domain.
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+    clock-controller@ad00000 {
+      compatible = "qcom,sm7150-camcc";
+      reg = <0xad00000 0x10000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/clock/qcom,sm7150-camcc.h b/include/dt-bindings/clock/qcom,sm7150-camcc.h
new file mode 100644
index 000000000000..cc187e40fbc0
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm7150-camcc.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM7150_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM7150_H
+
+/* Hardware clocks */
+#define CAM_CC_PLL0_OUT_EVEN					0
+#define CAM_CC_PLL0_OUT_ODD					1
+#define CAM_CC_PLL1_OUT_EVEN					2
+#define CAM_CC_PLL2_OUT_EARLY					3
+#define CAM_CC_PLL3_OUT_EVEN					4
+#define CAM_CC_PLL4_OUT_EVEN					5
+
+/* CAM_CC clock registers */
+#define CAM_CC_PLL0						6
+#define CAM_CC_PLL1						7
+#define CAM_CC_PLL2						8
+#define CAM_CC_PLL2_OUT_AUX					9
+#define CAM_CC_PLL2_OUT_MAIN					10
+#define CAM_CC_PLL3						11
+#define CAM_CC_PLL4						12
+#define CAM_CC_BPS_AHB_CLK					13
+#define CAM_CC_BPS_AREG_CLK					14
+#define CAM_CC_BPS_AXI_CLK					15
+#define CAM_CC_BPS_CLK						16
+#define CAM_CC_BPS_CLK_SRC					17
+#define CAM_CC_CAMNOC_AXI_CLK					18
+#define CAM_CC_CAMNOC_AXI_CLK_SRC				19
+#define CAM_CC_CAMNOC_DCD_XO_CLK				20
+#define CAM_CC_CCI_0_CLK					21
+#define CAM_CC_CCI_0_CLK_SRC					22
+#define CAM_CC_CCI_1_CLK					23
+#define CAM_CC_CCI_1_CLK_SRC					24
+#define CAM_CC_CORE_AHB_CLK					25
+#define CAM_CC_CPAS_AHB_CLK					26
+#define CAM_CC_CPHY_RX_CLK_SRC					27
+#define CAM_CC_CSI0PHYTIMER_CLK					28
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC				29
+#define CAM_CC_CSI1PHYTIMER_CLK					30
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC				31
+#define CAM_CC_CSI2PHYTIMER_CLK					32
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC				33
+#define CAM_CC_CSI3PHYTIMER_CLK					34
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC				35
+#define CAM_CC_CSIPHY0_CLK					36
+#define CAM_CC_CSIPHY1_CLK					37
+#define CAM_CC_CSIPHY2_CLK					38
+#define CAM_CC_CSIPHY3_CLK					39
+#define CAM_CC_FAST_AHB_CLK_SRC					40
+#define CAM_CC_FD_CORE_CLK					41
+#define CAM_CC_FD_CORE_CLK_SRC					42
+#define CAM_CC_FD_CORE_UAR_CLK					43
+#define CAM_CC_ICP_AHB_CLK					44
+#define CAM_CC_ICP_CLK						45
+#define CAM_CC_ICP_CLK_SRC					46
+#define CAM_CC_IFE_0_AXI_CLK					47
+#define CAM_CC_IFE_0_CLK					48
+#define CAM_CC_IFE_0_CLK_SRC					49
+#define CAM_CC_IFE_0_CPHY_RX_CLK				50
+#define CAM_CC_IFE_0_CSID_CLK					51
+#define CAM_CC_IFE_0_CSID_CLK_SRC				52
+#define CAM_CC_IFE_0_DSP_CLK					53
+#define CAM_CC_IFE_1_AXI_CLK					54
+#define CAM_CC_IFE_1_CLK					55
+#define CAM_CC_IFE_1_CLK_SRC					56
+#define CAM_CC_IFE_1_CPHY_RX_CLK				57
+#define CAM_CC_IFE_1_CSID_CLK					58
+#define CAM_CC_IFE_1_CSID_CLK_SRC				59
+#define CAM_CC_IFE_1_DSP_CLK					60
+#define CAM_CC_IFE_LITE_CLK					61
+#define CAM_CC_IFE_LITE_CLK_SRC					62
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK				63
+#define CAM_CC_IFE_LITE_CSID_CLK				64
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC				65
+#define CAM_CC_IPE_0_AHB_CLK					66
+#define CAM_CC_IPE_0_AREG_CLK					67
+#define CAM_CC_IPE_0_AXI_CLK					68
+#define CAM_CC_IPE_0_CLK					69
+#define CAM_CC_IPE_0_CLK_SRC					70
+#define CAM_CC_IPE_1_AHB_CLK					71
+#define CAM_CC_IPE_1_AREG_CLK					72
+#define CAM_CC_IPE_1_AXI_CLK					73
+#define CAM_CC_IPE_1_CLK					74
+#define CAM_CC_JPEG_CLK						75
+#define CAM_CC_JPEG_CLK_SRC					76
+#define CAM_CC_LRME_CLK						77
+#define CAM_CC_LRME_CLK_SRC					78
+#define CAM_CC_MCLK0_CLK					79
+#define CAM_CC_MCLK0_CLK_SRC					80
+#define CAM_CC_MCLK1_CLK					81
+#define CAM_CC_MCLK1_CLK_SRC					82
+#define CAM_CC_MCLK2_CLK					83
+#define CAM_CC_MCLK2_CLK_SRC					84
+#define CAM_CC_MCLK3_CLK					85
+#define CAM_CC_MCLK3_CLK_SRC					86
+#define CAM_CC_SLEEP_CLK					87
+#define CAM_CC_SLEEP_CLK_SRC					88
+#define CAM_CC_SLOW_AHB_CLK_SRC					89
+#define CAM_CC_XO_CLK_SRC					90
+
+/* CAM_CC GDSCRs */
+#define CAM_CC_BPS_GDSC						0
+#define CAM_CC_IFE_0_GDSC					1
+#define CAM_CC_IFE_1_GDSC					2
+#define CAM_CC_IPE_0_GDSC					3
+#define CAM_CC_IPE_1_GDSC					4
+#define CAM_CC_TITAN_TOP_GDSC					5
+
+#endif
