From patchwork Fri Feb 16 03:58:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 773467 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B642101C4; Fri, 16 Feb 2024 03:59:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708056001; cv=none; b=fG5GIluWmpN4bLdGWbDOtnsZcaYIP1MAxQmpCwANbXg+OuqnLEFD7KSAKHsZi2X114oZI66TTBPoi7kNQ1JrlPsYxwUvi1dusClCSzzGaV9npa00F3fbJ4ZSrytW8QIvsniYMgzc2vKDdOqA4++6wV/gavGqKNSLZJstb/w9T7c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708056001; c=relaxed/simple; bh=dkqdQuJ8Rq6+dAJb34C+xzhHLB/mL2WN/jcr5GLTyZA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=P7HOHRfIF/gNWAw+0KSkZz5e3ejnu9Bd3l0GgzvyZnjKssDRkQhhfAAQeUPPpLZVJzyflh8tYPwWAEaTjfsRTB+h5icnAdu0JcKBlbnYf1Olv6ABa3O1bTSZ98CyRR2HYUUSqbkGroINUd07vTH2RE488TXgNcusxwH06Evd/ig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=GrN7oPcg; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GrN7oPcg" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41G3lT7j020169; Fri, 16 Feb 2024 03:59:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=AdFyybXCQxALpHCh7Q4a DrMz/YV1catRW10h9gq82qw=; b=GrN7oPcgDXA6R4ayY+Ntyyg9C1KUeEvgmvDB a2tgp/FHSX+BgwEJPxt4dnNe6ysm8gMUVDZq4OFl9goZ9FhvEigFrHQWEFUovv5M WnmeYLvHS+TwNiqTBnC1JBiCsWhdJ/ywXfoW8saot5shos5NnNUCnaes/Vf/16Sp RP8b+2XTmrM2imM8OzSWoi3nJKG38bV+zMcuGa5f/6/QRkLK+SA/d06vBEGVQHpZ cyQA7kOYbWyrxJc1DzU0HwRz3dJzxqPSGdnw5Dwk2+uq5pXHeN5qnxDdX5xzDAj1 JcVy+Dgjw+uGQI5m3kfCqZ0mUVby7t9oGr7/4S9g/P1y+MLNLg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wa03r80ga-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Feb 2024 03:59:34 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41G3xXXh024875 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Feb 2024 03:59:33 GMT Received: from hu-wcheng-lv.qualcomm.com (10.49.16.6) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 15 Feb 2024 19:59:33 -0800 From: Wesley Cheng To: , , , , , , , , , , , , , , CC: , , , , , , , Mathias Nyman , Wesley Cheng Subject: [PATCH v16 02/50] xhci: Add helper to set an interrupters interrupt moderation interval Date: Thu, 15 Feb 2024 19:58:35 -0800 Message-ID: <20240216035923.23392-3-quic_wcheng@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240216035923.23392-1-quic_wcheng@quicinc.com> References: <20240216035923.23392-1-quic_wcheng@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BWNKkF7GawaJrLMKMwyDxo9zn0izUME6 X-Proofpoint-GUID: BWNKkF7GawaJrLMKMwyDxo9zn0izUME6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_03,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 adultscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402160031 From: Mathias Nyman Add a helper to set the interrupt moderation interval for an interrupter. Each interrupter can have its own moderation value. Hardware has a 16bit register for the moderation value, each step is 250ns. Helper function imod_interval argument is in nanoseconds. Values from 0 to 16383750 (250 x 0xffff) are accepted. 0 means no interrupt throttling. Change-Id: I28f3ee1692b00a36767c8e406db651cbf3ce30cf Signed-off-by: Mathias Nyman Signed-off-by: Wesley Cheng --- drivers/usb/host/xhci.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 0886829d53e5..b405b8236134 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -346,6 +346,23 @@ static int xhci_disable_interrupter(struct xhci_interrupter *ir) return 0; } +/* interrupt moderation interval imod_interval in nanoseconds */ +static int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, + u32 imod_interval) +{ + u32 imod; + + if (!ir || !ir->ir_set || imod_interval > U16_MAX * 250) + return -EINVAL; + + imod = readl(&ir->ir_set->irq_control); + imod &= ~ER_IRQ_INTERVAL_MASK; + imod |= (imod_interval / 250) & ER_IRQ_INTERVAL_MASK; + writel(imod, &ir->ir_set->irq_control); + + return 0; +} + static void compliance_mode_recovery(struct timer_list *t) { struct xhci_hcd *xhci; @@ -528,7 +545,6 @@ static int xhci_run_finished(struct xhci_hcd *xhci) */ int xhci_run(struct usb_hcd *hcd) { - u32 temp; u64 temp_64; int ret; struct xhci_hcd *xhci = hcd_to_xhci(hcd); @@ -551,12 +567,7 @@ int xhci_run(struct usb_hcd *hcd) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "ERST deq = 64'h%0lx", (long unsigned int) temp_64); - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Set the interrupt modulation register"); - temp = readl(&ir->ir_set->irq_control); - temp &= ~ER_IRQ_INTERVAL_MASK; - temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK; - writel(temp, &ir->ir_set->irq_control); + xhci_set_interrupter_moderation(ir, xhci->imod_interval); if (xhci->quirks & XHCI_NEC_HOST) { struct xhci_command *command;