From patchwork Fri Feb 16 03:58:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 773466 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14F7CFC1C; Fri, 16 Feb 2024 03:59:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708056001; cv=none; b=kJBZjvy7/DZ8yaqBesX4nEmfpql1csnu8J4Pi9QVGoRljwT4y9IncU5JETnPu0hoAbzObbWvpbHk3LU0ln7BBCJ6kxphTrsoK94svBHUubjXhu5H3URaGCP0ac/yJst1GA2czvwRUlKCSjPV4hSOxOUZ95aqywEvHRGv2jUlRmQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708056001; c=relaxed/simple; bh=I90H/5vbggXdrDvtctuwCY/Is7nOzbX/DC4vWzUEKVg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=scV8au6wgvb/qPH7y5myht3b1bo9r65082IU5BcHjDnuOHW3jxVxJUvQaKz+3AHnG2eeRYb+oj+32Qm0ZBliZI1FVyrw0j4VRIRHam+KvNb1ev84kxuiDZJTt0FYW3GacMt4pPGC2SX58KBlnnUYLLo6YsvDTqqwBaas4eT6Vhk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=VZgJQcZk; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="VZgJQcZk" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41G3SW5S008606; Fri, 16 Feb 2024 03:59:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=osg1G/0pQt/wMvzL8jkB cb958VO/8oIySaPDKOFKZWg=; b=VZgJQcZk06EDmnp/hvPiv/g2KDKUM89AaIzh PC1G4QVkWIERhqOqD5beSnyhW69NRIx/sLyBoirls6GNVW+K8mC9DUBpAE/tbwKB 3wQiEYytQ/0EdZMMi+j51zZtAcH2MbcK881SXtbN1Vt45vpyrFTelOsWYdBVAYq8 6JEcb9tfYXKfu+g01ayZuTB4z5nQlsJbe0PcYkVddUbNXYcwMFcBOaHmysBsWEZ/ nw/a4YKfYe0Bo035ozPmFmKEmWBlfeUMUQwI1E0AYIy7Pnc7YqVwirWnxGzFHmXt Y5M4KEu3cG2+8uP3KawhKEX0TomUeT/pSWg9uxYFwQdkrStorg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w9435uvcc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Feb 2024 03:59:34 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41G3xXkK029621 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Feb 2024 03:59:33 GMT Received: from hu-wcheng-lv.qualcomm.com (10.49.16.6) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 15 Feb 2024 19:59:33 -0800 From: Wesley Cheng To: , , , , , , , , , , , , , , CC: , , , , , , , Mathias Nyman , Wesley Cheng Subject: [PATCH v16 01/50] xhci: Add interrupt pending autoclear flag to each interrupter Date: Thu, 15 Feb 2024 19:58:34 -0800 Message-ID: <20240216035923.23392-2-quic_wcheng@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240216035923.23392-1-quic_wcheng@quicinc.com> References: <20240216035923.23392-1-quic_wcheng@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fbQtikIzw_wLay61IGW7dvIOFo-cZXS3 X-Proofpoint-ORIG-GUID: fbQtikIzw_wLay61IGW7dvIOFo-cZXS3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_02,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 bulkscore=0 mlxlogscore=842 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402160030 From: Mathias Nyman Each interrupter has an interrupt pending (IP) bit that should be cleared in the interrupt handler. This is done automatically for systems using MSI/MSI-X interrupts. Secondary interrupters used by audio offload may not actually trigger MSI/MSI-X messages, so driver may need to clear the IP bit manually for these, even if the primary interrupter IP is cleared automatically. Add an ip_autoclear flag to each interrupter that driver can configure when requesting an interrupt for that xHC interrupter, and move the interrupt pending clearing code to its own helper function. Use this ip_autoclear flag instead of the current hcd->msi_enabled to check if IP flag is cleared by software. [Moved ip_autoclear into xhci and set based on msi_enabled -wcheng] Change-Id: I20ba965dca9c4e65ff12a03c81114769315f6065 Signed-off-by: Mathias Nyman Signed-off-by: Wesley Cheng --- drivers/usb/host/xhci-ring.c | 21 +++++++++++++++------ drivers/usb/host/xhci.c | 3 +++ drivers/usb/host/xhci.h | 1 + 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index f0d8a607ff21..3d9ec78bfb9f 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -3063,6 +3063,19 @@ static void xhci_update_erst_dequeue(struct xhci_hcd *xhci, xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue); } +/* Clear the interrupt pending bit for a specific interrupter. */ +static void xhci_clear_interrupt_pending(struct xhci_hcd *xhci, + struct xhci_interrupter *ir) +{ + if (!ir->ip_autoclear) { + u32 irq_pending; + + irq_pending = readl(&ir->ir_set->irq_pending); + irq_pending |= IMAN_IP; + writel(irq_pending, &ir->ir_set->irq_pending); + } +} + /* * xHCI spec says we can get an interrupt, and if the HC has an error condition, * we might get bad data out of the event ring. Section 4.10.2.7 has a list of @@ -3112,12 +3125,8 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) /* This is the handler of the primary interrupter */ ir = xhci->interrupters[0]; - if (!hcd->msi_enabled) { - u32 irq_pending; - irq_pending = readl(&ir->ir_set->irq_pending); - irq_pending |= IMAN_IP; - writel(irq_pending, &ir->ir_set->irq_pending); - } + + xhci_clear_interrupt_pending(xhci, ir); if (xhci->xhc_state & XHCI_STATE_DYING || xhci->xhc_state & XHCI_STATE_HALTED) { diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index c057c42c36f4..0886829d53e5 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -538,6 +538,9 @@ int xhci_run(struct usb_hcd *hcd) */ hcd->uses_new_polling = 1; + if (hcd->msi_enabled) + ir->ip_autoclear = true; + if (!usb_hcd_is_primary_hcd(hcd)) return xhci_run_finished(xhci); diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 32d27134cc48..36c3ba64da51 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1432,6 +1432,7 @@ struct xhci_interrupter { struct xhci_erst erst; struct xhci_intr_reg __iomem *ir_set; unsigned int intr_num; + bool ip_autoclear; /* For interrupter registers save and restore over suspend/resume */ u32 s3_irq_pending; u32 s3_irq_control;