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[34.125.199.175]) by smtp.gmail.com with UTF8SMTPSA id p6-20020a625b06000000b006db05eb1301sm1726988pfb.21.2024.02.09.23.10.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 23:10:06 -0800 (PST) From: Stephen Boyd To: chrome-platform@lists.linux.dev Cc: linux-kernel@vger.kernel.org, patches@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Douglas Anderson , Pin-yen Lin , Prashant Malani , Benson Leung , Tzung-Bi Shih Subject: [PATCH 16/22] platform/chrome: cros_typec_switch: Support orientation-switch Date: Fri, 9 Feb 2024 23:09:27 -0800 Message-ID: <20240210070934.2549994-17-swboyd@chromium.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240210070934.2549994-1-swboyd@chromium.org> References: <20240210070934.2549994-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Register an orientation switch with the typec subsystem when the 'orientation-switch' DT property is present. In these sorts of hardware designs, the DP phy lanes are wired directly to the usb-c-connector. The EC signals entry and exit of DP mode on the port, and the DP phy lanes are assigned to the pins based on the port orientation (normal or reverse). Stash the orientation of the port and simply wait for the atomic_check phase to request the desired DP lane assignment (normal or reverse). Don't restrict this to the presence of the mode-switch property because it's possible for this device to only be an orientation-switch, in which case the DP mode entry is signaled externally (e.g. through an HPD pin on the DP source). Cc: Prashant Malani Cc: Benson Leung Cc: Tzung-Bi Shih Cc: Cc: Pin-yen Lin Signed-off-by: Stephen Boyd --- drivers/platform/chrome/cros_typec_switch.c | 84 ++++++++++++++++++--- 1 file changed, 72 insertions(+), 12 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c index adcbf8f44c98..c22c2531327a 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -38,9 +38,11 @@ struct cros_typec_dp_bridge { struct cros_typec_port { int port_num; struct typec_mux_dev *mode_switch; + struct typec_switch_dev *orientation_switch; struct typec_retimer *retimer; size_t num_dp_lanes; u32 lane_mapping[USBC_LANES_COUNT]; + enum typec_orientation orientation; struct cros_typec_switch_data *sdata; }; @@ -245,6 +247,21 @@ static int cros_typec_mode_switch_set(struct typec_mux_dev *mode_switch, return 0; } +static int cros_typec_dp_port_orientation_set(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct cros_typec_port *port = typec_switch_get_drvdata(sw); + + /* + * Lane remapping is in cros_typec_dp_bridge_atomic_check(). Whenever + * an orientation changes HPD will go low and then high again so the + * atomic check handles the orientation change. + */ + port->orientation = orientation; + + return 0; +} + static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_retimer_state *state) { struct cros_typec_port *port = typec_retimer_get_drvdata(retimer); @@ -280,6 +297,21 @@ static int cros_typec_register_mode_switch(struct cros_typec_port *port, return PTR_ERR_OR_ZERO(port->mode_switch); } +static int cros_typec_register_orientation_switch(struct cros_typec_port *port, + struct fwnode_handle *fwnode) +{ + struct typec_switch_desc orientation_switch_desc = { + .fwnode = fwnode, + .drvdata = port, + .name = fwnode_get_name(fwnode), + .set = cros_typec_dp_port_orientation_set, + }; + + port->orientation_switch = typec_switch_register(port->sdata->dev, &orientation_switch_desc); + + return PTR_ERR_OR_ZERO(port->orientation_switch); +} + static int cros_typec_register_retimer(struct cros_typec_port *port, struct fwnode_handle *fwnode) { struct typec_retimer_desc retimer_desc = { @@ -328,17 +360,35 @@ static int dp_lane_to_typec_lane(unsigned int dp_lane) return -EINVAL; } -static int typec_to_dp_lane(unsigned int typec_lane) +static int typec_to_dp_lane(unsigned int typec_lane, + enum typec_orientation orientation) { - switch (typec_lane) { - case 0: - return 3; - case 1: - return 2; - case 2: - return 0; - case 3: - return 1; + switch (orientation) { + case TYPEC_ORIENTATION_NONE: + case TYPEC_ORIENTATION_NORMAL: + switch (typec_lane) { + case 0: + return 3; + case 1: + return 2; + case 2: + return 0; + case 3: + return 1; + } + break; + case TYPEC_ORIENTATION_REVERSE: + switch (typec_lane) { + case 0: + return 0; + case 1: + return 1; + case 2: + return 3; + case 3: + return 2; + } + break; } return -EINVAL; @@ -381,7 +431,7 @@ static int cros_typec_dp_bridge_atomic_check(struct drm_bridge *bridge, typec_lane = port->lane_mapping[typec_lane]; /* Map logical type-c lane to logical DP lane */ - in_lanes[i].logical = typec_to_dp_lane(typec_lane); + in_lanes[i].logical = typec_to_dp_lane(typec_lane, port->orientation); } return 0; @@ -509,6 +559,15 @@ static int cros_typec_register_port(struct cros_typec_switch_data *sdata, dev_dbg(dev, "Mode switch registered for index %u\n", index); } + if (fwnode_property_present(fwnode, "orientation-switch")) { + ret = cros_typec_register_orientation_switch(port, port_node); + if (ret) { + dev_err(dev, "Orientation switch register failed\n"); + goto out; + } + + dev_dbg(dev, "Orientation switch registered for index %u\n", index); + } out: if (np) @@ -556,7 +615,8 @@ static int cros_typec_register_switches(struct cros_typec_switch_data *sdata) } } - if (fwnode_property_present(devnode, "mode-switch")) { + if (fwnode_property_present(devnode, "mode-switch") || + fwnode_property_present(devnode, "orientation-switch")) { fwnode = fwnode_graph_get_endpoint_by_id(devnode, 0, 0, 0); if (fwnode) { ret = cros_typec_register_dp_bridge(sdata, fwnode);