From patchwork Sat Feb 10 01:51:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paloma Arellano X-Patchwork-Id: 771611 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC24C442A for ; Sat, 10 Feb 2024 01:52:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707529972; cv=none; b=hJN9epa2pD9O1v8RG2iG8rfK3KaiaxI9cSgo4I0X1Y+uJarhFr3NbWN/XTOxWKUV1MZEyHd/ki6M+vcuYVkzSOexpa25ulMhAT8UmCuGJOltB6b7L7iRDIb6P/tw+CTwupq4LFQyms1Ne/wJdCSXG+cDZDATJWwGiNqoxmj3RjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707529972; c=relaxed/simple; bh=3aUSTZtTCGXfLCz8awGD0xbCJ2qnWJWEbTj2vvenJGI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cboLSGv6uyZPYa0I0Su8mD63eP4rvmws1G8SXBerDNKAAS6pndzsMhhuPXQEbaw1l3PdlLeFkHhDJpTbTH4mimWLdQKxd3lZDXz8k750jA+io6LVuC0WVUvVvwy8nWWdV/WT7ZCSP+GR0BJB9lxCbY9Bw9CBz2nt3JcHy3aOzKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Smc+nguN; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Smc+nguN" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41A1m0H0024174; Sat, 10 Feb 2024 01:52:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=2ZrslyT/MmvhB3mFLrLBWr8zzoqK0YatDu4hnEu8ydk=; b=Sm c+nguNzrs8aIgyzcudwJVq01LM+05SHNNOAj65X6GMeOvuvU2Ltw23ir2ISO6TBz F0+MSlOGDD6v9JBx4uDjDD+2tNkmX/4aYUUNwXOVq5hxnbUSgIie+Urdvr9eqYkg mfVOjyPMwJEh6YchZN3ZNaRHpL/Jq1mSU1ANBOOuTqmnM4pbJVA4sZUliHbXpCdD LgW6q9+9I9xP6gicJxdG2BKy0WUGLXI+rCJKcDa8Pbx7UIzrysrLn6GajSYXpyX1 D9R3WWmwSb64fzZMcjSJP6a5CEWS0QwbKHcqXnOvk3wqXzyQCVBHlGKGC1Y6yrNt Csi4FaTNtjJS8U9QbVJA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w5gk2hxhc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 10 Feb 2024 01:52:39 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41A1qcDF027998 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 10 Feb 2024 01:52:38 GMT Received: from hu-parellan-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 9 Feb 2024 17:52:38 -0800 From: Paloma Arellano To: CC: Paloma Arellano , , , , , , , , , , , Subject: [PATCH v2 03/19] drm/msm/dpu: pass mode dimensions instead of fb size in CDM setup Date: Fri, 9 Feb 2024 17:51:54 -0800 Message-ID: <20240210015223.24670-4-quic_parellan@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240210015223.24670-1-quic_parellan@quicinc.com> References: <20240210015223.24670-1-quic_parellan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rTlsK2Snwh64liixHhApD_E9INVfcyhu X-Proofpoint-GUID: rTlsK2Snwh64liixHhApD_E9INVfcyhu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-10_01,2024-02-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 impostorscore=0 suspectscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402100012 Modify the output width and height parameters of hw_cdm to utilize the physical encoder's data instead of obtaining the information from the framebuffer. CDM is to be set up to utilize the actual output data since at CDM setup, there is no difference between the two sources. Changes in v2: - Move the modification of the dimensions for CDM setup to this new patch Signed-off-by: Paloma Arellano --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 4cd2d9e3131a4..ec9e053d3947d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -306,8 +306,8 @@ static void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc) memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg)); - cdm_cfg->output_width = wb_job->fb->width; - cdm_cfg->output_height = wb_job->fb->height; + cdm_cfg->output_width = phys_enc->cached_mode.hdisplay; + cdm_cfg->output_height = phys_enc->cached_mode.vdisplay; cdm_cfg->output_fmt = dpu_fmt; cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB; cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?