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Thu, 08 Feb 2024 07:23:09 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCV7YNfQNUlgav+Sj7V7E/rWNOqacgBwg/58IvZWg25XLvdPZHvXXXghAukrZn1e+HH+sE5FTN7pSCkLviRJt5vf/2woaw+c3TB3i0KFnLocXUUX+vZlfacw/OYcPCOP8ha4IOyiMqE9mXrn4Ogk0j0MIs3hgnzv+IJmf+1l04aTsbawSF8m0p1VWnD0WIVJcGqeMuKBJpW2667DGwZt40/jnzrs0KO6YfPTIYaSlqYcjEbw7xYB22yEeKvhYtlQ6dkiS8y3o607O62u3shXsfzdpGYpcDKdzmwE1FytZlh+ Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id ep8-20020a056512484800b00511549b15acsm25635lfb.123.2024.02.08.07.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 07:23:08 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 08 Feb 2024 17:23:08 +0200 Subject: [PATCH v4] drm/msm/dsi: Document DSC related pclk_rate and hdisplay calculations Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240208-fd_document_dsc_pclk_rate-v4-1-56fe59d0a2e0@linaro.org> X-B4-Tracking: v=1; b=H4sIANvxxGUC/zXM0QqDIBiG4VsJj2eUmdmOdh9jiNO/kpbGr4tFd O+TwU4+eA6+9yAR0EEk1+IgCJuLLvgMfimImbQfgTqbTVjFeMUqSQerbDDvBXxSNhq1mtesUCe gVgstWF/3shMk/1eEwX1+7fsje8Cw0DQh6H+xqfOwpu15V9ZM8lZIWlO7uIR7+dS4x2kO2+3lv MZQBhzJeX4BktRJi7IAAAA= To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3118; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=lSoN4c4dQ5GWOLY+G32I+ql9QdfGB1rpvCvoA8U1v4o=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlxPHcwgWs9T+m+hVHbJbJbSQqaMUUJYv/XNPP5 Vvegdcs1EKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZcTx3AAKCRCLPIo+Aiko 1XjrCACaCpbHCUdpJzaJfUSD4AVFocoo2MoARD/x8SnfIywSoJQTjmA723MqBvgvjsqI8bHRS2b xjuK3u2Rr+Ym6kkI0d/HRKd8WRzjMkxdjXac+VHKq4kZROH1kAlbFt9VK6ftpt4kGOYuOOMLQcp nw5P3uRNIOOtLMECGh/9GxIe26UiaC1EOvHYYg86VLVjZNseWSOxB2O69IijJ/7XCe7dgiTwspO agBk4zXFVH6v9bMGrttdkwpOCdcAdC7U+XuQ82CUcyvXhADwOqBbYSZ2JqVypAW7rm9KrFl05Dx LIx1JSAK21d85Ixj8TJbvjL3sWVlxZ7S9lZKNbkFJSiL4/F6 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Provide actual documentation for the pclk and hdisplay calculations in the case of DSC compression being used. Signed-off-by: Dmitry Baryshkov --- Changes since v3: - refresh rate -> transfer time (Abhinav) Changes since v2: - Followed suggestion by Abhinav and Marijn to improve documentatry comments. Changes since v1: - Converted dsi_adjust_pclk_for_compression() into kerneldoc (Marijn) - Added a pointer from dsi_timing_setup() docs to dsi_adjust_pclk_for_compression() (Marijn) - Fixed two typo (Marijn) --- drivers/gpu/drm/msm/dsi/dsi_host.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) --- base-commit: b1d3a0e70c3881d2f8cf6692ccf7c2a4fb2d030d change-id: 20240208-fd_document_dsc_pclk_rate-da6a62919876 Best regards, diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index deeecdfd6c4e..6a6f1a21705e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -529,6 +529,25 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->byte_clk); } +/** + * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case + * @mode: The selected mode for the DSI output + * @dsc: DRM DSC configuration for this DSI output + * + * Adjust the pclk rate by calculating a new hdisplay proportional to + * the compression ratio such that: + * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp + * + * Porches do not need to be adjusted: + * - For VIDEO mode they are not compressed by DSC and are passed as is. + * - For CMD mode there are no actual porches. Instead these fields + * currently represent the overhead to the image data transfer. As such, they + * are calculated for the final mode parameters (after the compression) and + * are not to be adjusted too. + * + * FIXME: Reconsider this if/when CMD mode handling is rewritten to use + * transfer time and data overhead as a starting point of the calculations. + */ static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, const struct drm_dsc_config *dsc) { @@ -951,8 +970,18 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) if (ret) return; - /* Divide the display by 3 but keep back/font porch and - * pulse width same + /* + * DPU sends 3 bytes per pclk cycle to DSI. If widebus is + * enabled, bus width is extended to 6 bytes. + * + * Calculate the number of pclks needed to transmit one line of + * the compressed data. + + * The back/font porch and pulse width are kept intact. For + * VIDEO mode they represent timing parameters rather than + * actual data transfer, see the documentation for + * dsi_adjust_pclk_for_compression(). For CMD mode they are + * unused anyway. */ h_total -= hdisplay; if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))