From patchwork Thu Jan 25 19:38:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paloma Arellano X-Patchwork-Id: 766493 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A4B6135A7C for ; Thu, 25 Jan 2024 19:39:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706211557; cv=none; b=q0jHxAsH2mWBLFo5qMh7zQrbFnALlAQFCdRoGRon1sBCzlayAE+fSCH49/bV5YZi//87845vucT60dcvUnAC6mAvM+jqi4DRRtGjOZwbbb/KKPJ12DwSd1YShumUuH3JTzHvZslrkRfVsLvXi9Dwj8gCqyfP3H8xWGmtxwtfEZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706211557; c=relaxed/simple; bh=gItLKoICJ8N6I2WLj4h3YZSYMA0wzUzRNEi1csOlnng=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qisfnsA9FKjd/rfj6LjQlw4Ip0nbQTHT4CRmbGvZZzoERfBSMxM40vSvKilV8iAt2wqgoMJqYPRxUa70oLk/diQ86HImQPp7Q633uIethn8chb5vahbBr8yA1/uZB0JrHol+hht5kNUzdoyTm8q/bjjcYSAHzaQXrFQxn0P3I7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=b10nux8b; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="b10nux8b" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40PJUbMm008263; Thu, 25 Jan 2024 19:39:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=AY9coDoPPWJIZax/mx6N0N3vAa4FWzEX+7YpgdAqO1c=; b=b1 0nux8bhHly3b6Fn06ixZX8sfPNsMwUHsKn+D0NrKVfWd5ws6q5/IAFq8EVFmz0Mf iacoT1cGJ1D6QNN6oOOkm1KxYHACjlyPdp1rr1RB6E5o3oSUnBiNxk0UkK18oS/0 n6u6ZjyzuIqzOXdLagnLKRGiM1KaKV+H04z4U4SDAgnh5cGfbymEJDXlCrboiDUN fBqbU6kf4K/POylvje+QlxHeFku5ixZb3820xJ1Q8C9oGwJmTw5JqQTix+m/aZDR F6v0dlwF/+cxwRHHcXmTVzbk+WTJrLDpc6szCL/fRXTC0cetgAoUs3J5p0u4Uy39 7VY+1P2dTyfHIdZTMQFg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vup5cshak-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jan 2024 19:39:09 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40PJd9qe013951 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 Jan 2024 19:39:09 GMT Received: from hu-parellan-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 25 Jan 2024 11:39:08 -0800 From: Paloma Arellano To: CC: Paloma Arellano , , , , , , , , , , , Subject: [PATCH 13/17] drm/msm/dp: enable SDP and SDE periph flush update Date: Thu, 25 Jan 2024 11:38:22 -0800 Message-ID: <20240125193834.7065-14-quic_parellan@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240125193834.7065-1-quic_parellan@quicinc.com> References: <20240125193834.7065-1-quic_parellan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: g8RbvmiLWgSjCdqpGFxboDLp8nHJUlnr X-Proofpoint-ORIG-GUID: g8RbvmiLWgSjCdqpGFxboDLp8nHJUlnr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-25_12,2024-01-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 mlxlogscore=529 clxscore=1015 bulkscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401190000 definitions=main-2401250142 DP controller can be setup to operate in either SDP update flush mode or peripheral flush mode based on the DP controller hardware version. Starting in DP v1.2, the hardware documents require the use of peripheral flush mode for SDP packets such as PPS OR VSC SDP packets. In-line with this guidance, lets program the DP controller to use peripheral flush mode starting DP v1.2 Signed-off-by: Paloma Arellano --- drivers/gpu/drm/msm/dp/dp_catalog.c | 18 ++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_catalog.h | 1 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 + drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ 4 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 7e4c68be23e56..b43083b9c2df6 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -446,6 +446,24 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); } +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog) +{ + u32 mainlink_ctrl; + u16 major = 0, minor = 0; + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + + mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + + dp_catalog_hw_revision(dp_catalog, &major, &minor); + if (major >= 1 && minor >= 2) + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; + else + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; + + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 6b757249c0698..1d57988aa6689 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -169,6 +169,7 @@ void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config); void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable); +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index ddd92a63d5a67..c375b36f53ce1 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -170,6 +170,7 @@ static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) dp_catalog_ctrl_lane_mapping(ctrl->catalog); dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); + dp_catalog_setup_peripheral_flush(ctrl->catalog); dp_ctrl_config_ctrl(ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 756ddf85b1e81..05a1009d2f678 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -102,6 +102,8 @@ #define DP_MAINLINK_CTRL_ENABLE (0x00000001) #define DP_MAINLINK_CTRL_RESET (0x00000002) #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP (0x00800000) +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE (0x01800000) #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) #define REG_DP_STATE_CTRL (0x00000004)