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Thu, 25 Jan 2024 21:05:12 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 25 Jan 2024 13:05:11 -0800 From: Bjorn Andersson Date: Thu, 25 Jan 2024 13:05:07 -0800 Subject: [PATCH v4 1/8] dt-bindings: clock: qcom: Allow VDD_GFX supply to GX Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240125-sa8295p-gpu-v4-1-7011c2a63037@quicinc.com> References: <20240125-sa8295p-gpu-v4-0-7011c2a63037@quicinc.com> In-Reply-To: <20240125-sa8295p-gpu-v4-0-7011c2a63037@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Johan Hovold CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706216711; l=1114; i=quic_bjorande@quicinc.com; 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Allow this to be described in the GPU clock controller binding. Signed-off-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index f369fa34e00c..f57aceddac6b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -53,6 +53,9 @@ properties: power-domains: maxItems: 1 + vdd-gfx-supply: + description: Regulator supply for the VDD_GFX pads + '#clock-cells': const: 1 @@ -74,6 +77,12 @@ required: - '#reset-cells' - '#power-domain-cells' +# Require that power-domains and vdd-gfx-supply are not both present +not: + required: + - power-domains + - vdd-gfx-supply + additionalProperties: false examples: