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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id r14-20020a2e994e000000b002ccb512da04sm1653936ljj.34.2024.01.16.04.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 04:25:53 -0800 (PST) From: Konrad Dybcio Date: Tue, 16 Jan 2024 13:25:44 +0100 Subject: [PATCH] arm64: dts: qcom: sm8450: Add missing interconnects to serial Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240116-topic-8450serial-v1-1-b685e6a5ad78@linaro.org> X-B4-Tracking: v=1; b=H4sIAMh1pmUC/x3MQQqAIBBA0avIrBMc0YiuEi3MxhoIC40IpLtnL f/i/QKZElOGXhRIdHHmPdbARoBfXVxI8lwbtNJGIbby3A/2sjNWfdJt0igd/GRJI05Q2ZEo8P0 vh/F5XlIJlItiAAAA To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Dmitry Baryshkov Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Georgi Djakov , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c The serial ports did not have their interconnect paths specified when they were first introduced. Fix that. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Fixes: f5837418479a ("arm64: dts: qcom: sm8450: add uart20 node") Reported-by: Krzysztof Kozlowski Suggested-by: Georgi Djakov Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) --- base-commit: 8d04a7e2ee3fd6aabb8096b00c64db0d735bc874 change-id: 20240116-topic-8450serial-402fcb5e211b Best regards, diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 01e4dfc4babd..06f183ef8c78 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1028,6 +1028,12 @@ uart20: serial@894000 { pinctrl-names = "default"; pinctrl-0 = <&qup_uart20_default>; interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; status = "disabled"; }; @@ -1420,6 +1426,12 @@ uart7: serial@99c000 { pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; status = "disabled"; }; };