From patchwork Sun Dec 31 00:43:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759253 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E43017D3 for ; Sun, 31 Dec 2023 00:44:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="b7TQCTU0" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-50e70b0b869so6192516e87.2 for ; Sat, 30 Dec 2023 16:44:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703983443; x=1704588243; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=f23f6k2NURR3hjj9IxLe37rVyBQBMzjyoSIDJiZdG1c=; b=b7TQCTU01353Cs+rN6nDFZJCAGkYBFJigKjuzmwDjlBymygrEAQ3xv/wA9UaDU+wQt G7YZJx5Epe+kyR7RCH1d22bqVl1BBVnySjc1fCuuSYQngqR1oRD5zOW3GIJrUDCHbv8M NInYadQF5DABkXpYYkBxNXS8oAjsSq8EBnoZNz8QyhbJ0UA6G7zXfUAMOPwqzAIjmaFY z+yhpLbo2qkDawZnJuTkd1tXBVcMmggkeq4a+KZ8ZzzxZ4HA/45UPWCI79bYv1WJKapA grJyVMQJz/DL9tduWYf4yBr46s5qts480v8v7T9NIVjS3BOA5jwnB7+zi8BjJXbQjUL4 Bkrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703983443; x=1704588243; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f23f6k2NURR3hjj9IxLe37rVyBQBMzjyoSIDJiZdG1c=; b=KD2RpQqIiNWIVm4nhvUhVYiYzrcjAsxweb0679hvKdbhZY3qn2cOErfzj1GT/upcHh SP2wmofBPz9TT7UB8SepLBWC9Mut/JWbPBqKV96YQcn6mxDjL8gr87Cu96y5mT5efwp9 vKIDYOMyuHdzLQUQGS5ugIepHgU9ox4jQkVwohm+DsqEoqzYMQOif7iIT1XJKLcoMvsX JCI0dt8GZRpoZpyWi7suseGBSjSBt9cL4E7NB35Ptebggilh2G2beQK6+uhbtEPXFhPY YU2FyYLIDnrui9sE8xdYiIy4+8SomOKETDSZXWu0XzySyVZ0z4Zf93jfgOMOtStn6iGW TcRg== X-Gm-Message-State: AOJu0YzNk7H6MV0O3tRnlWAhP2U6UV18oCk/VWBs8fYiagZ/JXI7/Xmj av/bbqaxg0jQejav6i2rqiE98LFYyMNPgA== X-Google-Smtp-Source: AGHT+IGo3QVbbuztsYi/hkw7G7J2Q7A7Wjez+g7zFg/0SAjx4ORvy+3ZbCef4K3kR93437TeWEbP1Q== X-Received: by 2002:a19:6549:0:b0:50e:558e:1259 with SMTP id c9-20020a196549000000b0050e558e1259mr5058894lfj.19.1703983443757; Sat, 30 Dec 2023 16:44:03 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id n13-20020a05651203ed00b0050e84be8127sm1295995lfq.101.2023.12.30.16.44.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Dec 2023 16:44:03 -0800 (PST) From: Dmitry Baryshkov Date: Sun, 31 Dec 2023 02:43:56 +0200 Subject: [PATCH v2 09/15] drm/msm/dp: move phy_configure_opts to dp_ctrl Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231231-dp-power-parser-cleanup-v2-9-fc3e902a6f5b@linaro.org> References: <20231231-dp-power-parser-cleanup-v2-0-fc3e902a6f5b@linaro.org> In-Reply-To: <20231231-dp-power-parser-cleanup-v2-0-fc3e902a6f5b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Kuogee Hsieh , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Bjorn Andersson , Konrad Dybcio X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=6449; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=JHMCbSPE7gZXRzZ8Yh8uYk+Fdg3YzXkUqA/+AlXGaYM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlkLlKHK7IATSmw6bh0J/WgmalOpsadKPT+lVOo 2Vd8ZEHEHiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZC5SgAKCRCLPIo+Aiko 1SRKB/9OTjUhJi3PtlZUs+9HvdLVY9H3o+ZsUSwd2PWuq81ipwfpsICrlCdZqQ+2jZ8qd2gcQM7 c3ihVMqCs73XElAlVBbKBSwswP1XVM63TyKnQs3K2IKaFTrDQ1ON3/FSATz05djdq5mJGvWWMT3 WK4upsYVckKgMKxQHkQumi+XeiXA5YXPPoEbpRwuzIy/LvkdbqIGpo6roRLAQldSZYU20wy6BjI ei0xAr1UKWaKOabbV5hZjFuooMDMDSvDj81ZDrzgkut7eb266e/FU/nM3ncscRUGHrfsVQfoOg1 VzGFcy6i8Laa2y6V5A+YfYi9TcWuihF+8/tbQ3/bqukO1N2J X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A There is little point in sharing phy configuration structure between several modules. Move it to dp_ctrl, which becomes the only submodule re-configuring the PHY. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/dp/dp_catalog.c | 19 ----------------- drivers/gpu/drm/msm/dp/dp_catalog.h | 2 -- drivers/gpu/drm/msm/dp/dp_ctrl.c | 41 ++++++++++++++++++++++++------------- drivers/gpu/drm/msm/dp/dp_parser.h | 3 --- 4 files changed, 27 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 5142aeb705a4..e07651768805 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -765,25 +765,6 @@ void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog) dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); } -int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, - u8 v_level, u8 p_level) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - struct dp_io *dp_io = catalog->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; - - /* TODO: Update for all lanes instead of just first one */ - opts_dp->voltage[0] = v_level; - opts_dp->pre[0] = p_level; - opts_dp->set_voltages = 1; - phy_configure(phy, &dp_io->phy_opts); - opts_dp->set_voltages = 0; - - return 0; -} - void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, u32 pattern) { diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 38786e855b51..ba7c62ba7ca3 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -111,8 +111,6 @@ void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter); u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog); u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog); -int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level, - u8 p_level); int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog); u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog, diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index e367eb8e5bea..4aea72a2b8e8 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -87,6 +87,8 @@ struct dp_ctrl_private { struct clk *pixel_clk; + union phy_configure_opts phy_opts; + struct completion idle_comp; struct completion psr_op_comp; struct completion video_comp; @@ -1017,6 +1019,21 @@ static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) return ret; } +static int dp_ctrl_set_vx_px(struct dp_ctrl_private *ctrl, + u8 v_level, u8 p_level) +{ + union phy_configure_opts *phy_opts = &ctrl->phy_opts; + + /* TODO: Update for all lanes instead of just first one */ + phy_opts->dp.voltage[0] = v_level; + phy_opts->dp.pre[0] = p_level; + phy_opts->dp.set_voltages = 1; + phy_configure(ctrl->parser->io.phy, phy_opts); + phy_opts->dp.set_voltages = 0; + + return 0; +} + static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) { struct dp_link *link = ctrl->link; @@ -1029,7 +1046,7 @@ static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "voltage level: %d emphasis level: %d\n", voltage_swing_level, pre_emphasis_level); - ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog, + ret = dp_ctrl_set_vx_px(ctrl, voltage_swing_level, pre_emphasis_level); if (ret) @@ -1425,16 +1442,14 @@ static void dp_ctrl_link_clk_disable(struct dp_ctrl *dp_ctrl) static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) { int ret = 0; - struct dp_io *dp_io = &ctrl->parser->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; + struct phy *phy = ctrl->parser->io.phy; const u8 *dpcd = ctrl->panel->dpcd; - opts_dp->lanes = ctrl->link->link_params.num_lanes; - opts_dp->link_rate = ctrl->link->link_params.rate / 100; - opts_dp->ssc = drm_dp_max_downspread(dpcd); + ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; + ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; + ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); - phy_configure(phy, &dp_io->phy_opts); + phy_configure(phy, &ctrl->phy_opts); phy_power_on(phy); dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); @@ -1572,14 +1587,12 @@ static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) { + struct phy *phy = ctrl->parser->io.phy; int ret = 0; - struct dp_io *dp_io = &ctrl->parser->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); - opts_dp->lanes = ctrl->link->link_params.num_lanes; - phy_configure(phy, &dp_io->phy_opts); + ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; + phy_configure(phy, &ctrl->phy_opts); /* * Disable and re-enable the mainlink clock since the * link clock might have been adjusted as part of the @@ -1659,7 +1672,7 @@ static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); - if (dp_catalog_ctrl_update_vx_px(ctrl->catalog, + if (dp_ctrl_set_vx_px(ctrl, ctrl->link->phy_params.v_level, ctrl->link->phy_params.p_level)) { DRM_ERROR("Failed to set v/p levels\n"); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index cad82c4d07da..b28052e87101 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -7,8 +7,6 @@ #define _DP_PARSER_H_ #include -#include -#include #include "msm_drv.h" @@ -37,7 +35,6 @@ struct dss_io_data { struct dp_io { struct dss_io_data dp_controller; struct phy *phy; - union phy_configure_opts phy_opts; }; /**