From patchwork Fri Dec 29 22:56:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759116 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C4BD15488 for ; Fri, 29 Dec 2023 22:56:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G7L7B1+o" Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-50e78f1f41fso4361304e87.2 for ; Fri, 29 Dec 2023 14:56:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703890617; x=1704495417; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vg8yJRW4p2x0lwIZbztyFSj/Gr+GANMZijc9xIjNZSM=; b=G7L7B1+oBXFHc8+IXt5BHYKynxULsl/LujjXYZx0N566Gbr2DoBnuVijlpVdkedq2/ SWcV7lzDCDLQbAbN5Vkek0woqUUfV03GrQj/Ew5vE3rVXIUv7Jw4Cvy4JREkzIUeY0Cm 2HBWo7QVOQimZOHJsvjBF7Ii8tY15yQ+2ztaQrqANKZ/BzTgUiThOAUtym2ngaIZj3h9 J9FlHH5eyGiWDaJ6BmpfRMHoTqbhm+8g12/HPxvI+9lE7F0cWYeCrUJQqr9e/bn4lCiw H5JAjmVfBLdMNyeASyLrsrkqicQsEZBQLH+ckJxMCKO4lw6JBa3Aun+jIpm7GBzzV8Ha 7hdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703890617; x=1704495417; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vg8yJRW4p2x0lwIZbztyFSj/Gr+GANMZijc9xIjNZSM=; b=nw9tU0HfWjy5EpHo8UFziQXx05E4BQdyvrXYHd+xuucahqimkigJm51s6DN6SFXNp3 5xySmGlUt7Vx4toXH1mV9GB7dP/f8QXX6WGg8W6sIZ3YpN7U7Ef90rVCZX3wit0U9NJl ycVaNK4Ctv073/f9mh4VsY6EsXmPQgagg9qCtZp6/yFDGIbf6e1W5epEXATLwKiZQxV7 ahFaXyROxeaT4ol88vG82CpWaYfbXDI+zvePlWJobKfR3Y+GbvJTuyZWwJLKPBXCEFVF an9P00xP/wOjq5crBLT2UQKSW8kihsXhm22VZS34z9+T83li3m1B9jOCSVyM3cNaNu1G v7TQ== X-Gm-Message-State: AOJu0Yz9RFV6CvRJcBgS26WeDFCkoilBVTTdSVtjqZn9pYTvdMexYrqd 50zrt9iJ4eP5guMN0+0zIGE5PrrBM5+3pg== X-Google-Smtp-Source: AGHT+IE2+chXc8Xc2K7q3QDqlEC3TxrQNe4abfwdDHsAa8dcvEQPT7I//JGkIdrmvCLe4AVuh9FNig== X-Received: by 2002:a19:ac06:0:b0:50e:4acb:3d0d with SMTP id g6-20020a19ac06000000b0050e4acb3d0dmr4349535lfc.47.1703890617710; Fri, 29 Dec 2023 14:56:57 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id j26-20020ac2455a000000b0050e7f5794cbsm1326952lfm.309.2023.12.29.14.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Dec 2023 14:56:57 -0800 (PST) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Kuogee Hsieh , Sankeerth Billakanti Cc: Bjorn Andersson , Konrad Dybcio , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 08/14] drm/msm/dp: move phy_configure_opts to dp_ctrl Date: Sat, 30 Dec 2023 00:56:44 +0200 Message-Id: <20231229225650.912751-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231229225650.912751-1-dmitry.baryshkov@linaro.org> References: <20231229225650.912751-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There is little point in sharing phy configuration structure between several modules. Move it to dp_ctrl, which becomes the only submodule re-configuring the PHY. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 19 ------------- drivers/gpu/drm/msm/dp/dp_catalog.h | 2 -- drivers/gpu/drm/msm/dp/dp_ctrl.c | 41 +++++++++++++++++++---------- drivers/gpu/drm/msm/dp/dp_parser.h | 3 --- 4 files changed, 27 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 5142aeb705a4..e07651768805 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -765,25 +765,6 @@ void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog) dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); } -int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, - u8 v_level, u8 p_level) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - struct dp_io *dp_io = catalog->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; - - /* TODO: Update for all lanes instead of just first one */ - opts_dp->voltage[0] = v_level; - opts_dp->pre[0] = p_level; - opts_dp->set_voltages = 1; - phy_configure(phy, &dp_io->phy_opts); - opts_dp->set_voltages = 0; - - return 0; -} - void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, u32 pattern) { diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 38786e855b51..ba7c62ba7ca3 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -111,8 +111,6 @@ void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter); u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog); u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog); -int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level, - u8 p_level); int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog); u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog, diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 9b59a29547c0..3bb8bd83fff4 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -87,6 +87,8 @@ struct dp_ctrl_private { struct dss_module_power mp[DP_MAX_PM]; struct clk *pixel_clk; + union phy_configure_opts phy_opts; + struct completion idle_comp; struct completion psr_op_comp; struct completion video_comp; @@ -1026,6 +1028,21 @@ static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) return ret; } +static int dp_ctrl_set_vx_px(struct dp_ctrl_private *ctrl, + u8 v_level, u8 p_level) +{ + union phy_configure_opts *phy_opts = &ctrl->phy_opts; + + /* TODO: Update for all lanes instead of just first one */ + phy_opts->dp.voltage[0] = v_level; + phy_opts->dp.pre[0] = p_level; + phy_opts->dp.set_voltages = 1; + phy_configure(ctrl->parser->io.phy, phy_opts); + phy_opts->dp.set_voltages = 0; + + return 0; +} + static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) { struct dp_link *link = ctrl->link; @@ -1038,7 +1055,7 @@ static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "voltage level: %d emphasis level: %d\n", voltage_swing_level, pre_emphasis_level); - ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog, + ret = dp_ctrl_set_vx_px(ctrl, voltage_swing_level, pre_emphasis_level); if (ret) @@ -1340,16 +1357,14 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) { int ret = 0; - struct dp_io *dp_io = &ctrl->parser->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; + struct phy *phy = ctrl->parser->io.phy; const u8 *dpcd = ctrl->panel->dpcd; - opts_dp->lanes = ctrl->link->link_params.num_lanes; - opts_dp->link_rate = ctrl->link->link_params.rate / 100; - opts_dp->ssc = drm_dp_max_downspread(dpcd); + ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; + ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; + ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); - phy_configure(phy, &dp_io->phy_opts); + phy_configure(phy, &ctrl->phy_opts); phy_power_on(phy); dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); @@ -1488,13 +1503,11 @@ static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) { int ret = 0; - struct dp_io *dp_io = &ctrl->parser->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; + struct phy *phy = ctrl->parser->io.phy; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); - opts_dp->lanes = ctrl->link->link_params.num_lanes; - phy_configure(phy, &dp_io->phy_opts); + ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; + phy_configure(phy, &ctrl->phy_opts); /* * Disable and re-enable the mainlink clock since the * link clock might have been adjusted as part of the @@ -1580,7 +1593,7 @@ static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); - if (dp_catalog_ctrl_update_vx_px(ctrl->catalog, + if (dp_ctrl_set_vx_px(ctrl, ctrl->link->phy_params.v_level, ctrl->link->phy_params.p_level)) { DRM_ERROR("Failed to set v/p levels\n"); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index cad82c4d07da..b28052e87101 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -7,8 +7,6 @@ #define _DP_PARSER_H_ #include -#include -#include #include "msm_drv.h" @@ -37,7 +35,6 @@ struct dss_io_data { struct dp_io { struct dss_io_data dp_controller; struct phy *phy; - union phy_configure_opts phy_opts; }; /**