From patchwork Wed Dec 20 06:02:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 757175 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42EA110A36; Wed, 20 Dec 2023 06:03:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="B3rdraeO" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BK61KHh019634; Wed, 20 Dec 2023 06:02:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=JrVRyZ96yUrBQQjgIufD AqTRtO5j55EQwDj2xFPFFbM=; b=B3rdraeOmddSFxlwGKM4YQleLbKUBC/VB+N3 cSs6rx54H76BHCJ93Rw7R0JEN9AQOiyr7eknvZS75gSHODituF0aYpkXb6BJJ9z6 158vQwgMeatKzTizXHEijazKFu2Z2DKteeOJArb6S3lEkw+k38luLNBRJzFcG90i nf3pyJ41+EgRQSzV1JxXiNuotHpdC4xQ6nxI9uz4/Lgnnq/GRCuBxqmXUDU44DaX 1T0Hzr1TrCL5/Ox/V7+6vgGbyYW/CPhYW0TNjSwY2oN9KrGPi6Tkie7+3z60CwTd x+eqycuII8RVp0x8hCi6Z93HC4SPGjfW3BG3IUq4zw56RN4lZA== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v3tmm0040-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 06:02:47 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BK62kFM023280 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 06:02:47 GMT Received: from hu-c-gdjako-lv.qualcomm.com (10.49.16.6) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 19 Dec 2023 22:02:46 -0800 From: Georgi Djakov To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH v3 2/9] iommu/arm-smmu-qcom: Add support for TBUs Date: Tue, 19 Dec 2023 22:02:29 -0800 Message-ID: <20231220060236.18600-3-quic_c_gdjako@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231220060236.18600-1-quic_c_gdjako@quicinc.com> References: <20231220060236.18600-1-quic_c_gdjako@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0yXttM7_80DqHKU_wIo5zAGw4ZibtNZn X-Proofpoint-ORIG-GUID: 0yXttM7_80DqHKU_wIo5zAGw4ZibtNZn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 impostorscore=0 mlxscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 adultscore=0 malwarescore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312200038 The ARM MMU-500 implements a Translation Buffer Unit (TBU) for each connected master besides a single TCU which controls and manages the address translations. Allow the Qualcomm SMMU driver to probe for any TBU devices that can provide additional debug features like triggering transactions, logging outstanding transactions, snapshot capture etc. The primary use-case would be to get information from a TBU and print it during a context fault. Signed-off-by: Georgi Djakov --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 4 +++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 8b04ece00420..581401d6c18a 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -1,12 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved */ #include #include #include #include +#include #include #include "arm-smmu.h" @@ -446,6 +448,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, const struct device_node *np = smmu->dev->of_node; const struct arm_smmu_impl *impl; struct qcom_smmu *qsmmu; + int ret; if (!data) return ERR_PTR(-EINVAL); @@ -469,6 +472,12 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, qsmmu->smmu.impl = impl; qsmmu->cfg = data->cfg; + INIT_LIST_HEAD(&qsmmu->tbu_list); + mutex_init(&qsmmu->tbu_list_lock); + ret = devm_of_platform_populate(smmu->dev); + if (ret) + return ERR_PTR(ret); + return &qsmmu->smmu; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h index 593910567b88..2164a9cf3dde 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _ARM_SMMU_QCOM_H @@ -12,6 +12,8 @@ struct qcom_smmu { bool bypass_quirk; u8 bypass_cbndx; u32 stall_enabled; + struct mutex tbu_list_lock; /* protects tbu_list */ + struct list_head tbu_list; }; enum qcom_smmu_impl_reg_offset {