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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Starting from SM8550, the SSPP & WB clock controls are moved the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT" downstream. An optional clk_ctrl struct is added to the SSPP & WB caps, which can be used by the setup_clk_force_ctrl() op. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 4 ++++ 5 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 6c9634209e9f..d9e8673e46f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -505,6 +505,7 @@ struct dpu_ctl_cfg { * @sblk: SSPP sub-blocks information * @xin_id: bus client identifier * @clk_ctrl clock control identifier + * @clk_ctrl_reg local sspp clock control register * @type sspp type identifier */ struct dpu_sspp_cfg { @@ -512,6 +513,7 @@ struct dpu_sspp_cfg { const struct dpu_sspp_sub_blks *sblk; u32 xin_id; enum dpu_clk_ctrl_type clk_ctrl; + const struct dpu_clk_ctrl_reg *clk_ctrl_reg; u32 type; }; @@ -620,6 +622,7 @@ struct dpu_intf_cfg { * @format_list: list of formats supported by this writeback block * @num_formats: number of formats supported by this writeback block * @clk_ctrl: clock control identifier + * @clk_ctrl_reg local wb clock control register */ struct dpu_wb_cfg { DPU_HW_BLK_INFO; @@ -630,6 +633,7 @@ struct dpu_wb_cfg { const u32 *format_list; u32 num_formats; enum dpu_clk_ctrl_type clk_ctrl; + const struct dpu_clk_ctrl_reg *clk_ctrl_reg; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index f2192de93713..cc4c7141791f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -581,6 +581,14 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, dpu_setup_cdp(&ctx->hw, cdp_cntl_offset, fmt, enable); } +static bool dpu_hw_sspp_setup_clk_force_ctrl(struct dpu_hw_sspp *ctx, bool enable) +{ + if (!ctx->cap->clk_ctrl_reg) + return false; + + return dpu_hw_clk_force_ctrl(&ctx->hw, ctx->cap->clk_ctrl_reg, enable); +} + static void _setup_layer_ops(struct dpu_hw_sspp *c, unsigned long features) { @@ -589,6 +597,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c, c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress; c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill; c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; + c->ops.setup_clk_force_ctrl = dpu_hw_sspp_setup_clk_force_ctrl; if (test_bit(DPU_SSPP_QOS, &features)) { c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index cbf4f95ff0fd..4a77734e83a7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -11,6 +11,7 @@ #include "dpu_formats.h" struct dpu_hw_sspp; +struct dpu_hw_mdp; /** * Flags @@ -271,6 +272,14 @@ struct dpu_hw_sspp_ops { void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx, bool danger_safe_en); + /** + * setup_clk_force_ctrl - setup clock force control + * @ctx: Pointer to pipe context + * @enable: enable clock force if true + */ + bool (*setup_clk_force_ctrl)(struct dpu_hw_sspp *ctx, + bool enable); + /** * setup_histogram - setup histograms * @ctx: Pointer to pipe context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c index ebc416400382..045a4545a8c5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -175,11 +175,20 @@ static void dpu_hw_wb_bind_pingpong_blk( DPU_REG_WRITE(c, WB_MUX, mux_cfg); } +static bool dpu_hw_wb_setup_clk_force_ctrl(struct dpu_hw_wb *ctx, bool enable) +{ + if (!ctx->caps->clk_ctrl_reg) + return false; + + return dpu_hw_clk_force_ctrl(&ctx->hw, ctx->caps->clk_ctrl_reg, enable); +} + static void _setup_wb_ops(struct dpu_hw_wb_ops *ops, unsigned long features) { ops->setup_outaddress = dpu_hw_wb_setup_outaddress; ops->setup_outformat = dpu_hw_wb_setup_format; + ops->setup_clk_force_ctrl = dpu_hw_wb_setup_clk_force_ctrl; if (test_bit(DPU_WB_XY_ROI_OFFSET, &features)) ops->setup_roi = dpu_hw_wb_roi; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h index 2d7db2efa3d0..3734ca435e01 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h @@ -29,6 +29,7 @@ struct dpu_hw_wb_cfg { * @setup_outformat: setup output format of writeback block from writeback job * @setup_qos_lut: setup qos LUT for writeback block based on input * @setup_cdp: setup chroma down prefetch block for writeback block + * @setup_clk_force_ctrl: setup clock force control * @bind_pingpong_blk: enable/disable the connection with ping-pong block */ struct dpu_hw_wb_ops { @@ -48,6 +49,9 @@ struct dpu_hw_wb_ops { const struct dpu_format *fmt, bool enable); + bool (*setup_clk_force_ctrl)(struct dpu_hw_wb *ctx, + bool enable); + void (*bind_pingpong_blk)(struct dpu_hw_wb *ctx, const enum dpu_pingpong pp); };