diff mbox series

[3/4] arm64: dts: qcom: ipq9574: Add pwm support

Message ID 20231006045317.1056625-4-quic_devipriy@quicinc.com
State New
Headers show
Series Enable pwm support for IPQ5332 & IPQ9574 SoCs | expand

Commit Message

Devi Priya Oct. 6, 2023, 4:53 a.m. UTC 
The PWM is in the TCSR area. Make tcsr "simple-mfd" compatible
and add pwm as a child of tcsr.
Also, Enable pwm support in RDP418 of IPQ9574 SoC.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts | 12 ++++++++++++
 arch/arm64/boot/dts/qcom/ipq9574.dtsi       | 15 ++++++++++++++-
 2 files changed, 26 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
index 2b093e02637b..d275c98b4df7 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
@@ -43,6 +43,12 @@  &blsp1_uart2 {
 	status = "okay";
 };
 
+&pwm {
+	pinctrl-0 = <&pwm_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &rpm_requests {
 	regulators {
 		compatible = "qcom,rpm-mp5496-regulators";
@@ -79,6 +85,12 @@  &sleep_clk {
 };
 
 &tlmm {
+	pwm_pins: pwm-state {
+		pins = "gpio57";
+		function = "pwm";
+		drive-strength = <8>;
+	};
+
 	sdc_default_state: sdc-default-state {
 		clk-pins {
 			pins = "gpio5";
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 8a72ad4afd03..5465254fbdde 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -296,8 +296,21 @@  tcsr_mutex: hwlock@1905000 {
 		};
 
 		tcsr: syscon@1937000 {
-			compatible = "qcom,tcsr-ipq9574", "syscon";
+			compatible = "qcom,tcsr-ipq9574", "syscon", "simple-mfd";
 			reg = <0x01937000 0x21000>;
+			ranges = <0x0 0x01937000 0x21000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			pwm: pwm@a010 {
+				compatible = "qcom,ipq9574-pwm", "qcom,ipq6018-pwm";
+				reg = <0xa010 0x20>;
+				clocks = <&gcc GCC_ADSS_PWM_CLK>;
+				assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
+				assigned-clock-rates = <100000000>;
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
 		};
 
 		sdhc_1: mmc@7804000 {