From patchwork Wed Sep 20 06:54:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tengfei Fan X-Patchwork-Id: 724713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48A19CE79AD for ; Wed, 20 Sep 2023 06:56:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233464AbjITG4z (ORCPT ); Wed, 20 Sep 2023 02:56:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233520AbjITG4o (ORCPT ); Wed, 20 Sep 2023 02:56:44 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AF0C188; Tue, 19 Sep 2023 23:56:34 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38K5uUSw031527; Wed, 20 Sep 2023 06:56:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=f/x7VENveBXDJ0PWZ4R0R6S9TAflSTBkW8up2bquPeg=; b=ErUsMkZPIgvv9zM2BoCZf6s+jUR31FCEoIKsoGR0kmwfAbj9SRilu6+I2Mo2/ajQe2Fz Xx5NAcRiw02d+xIXjY8XVSf/B4jgyR+bDkx68D2YCHaXtXJTodL5ZBPpoYoLNUd5Hjt3 HAux9vMjTY6qlgX9W9XiST6C8S1SxWhyqrGhptMzVjAhhmHmGtzDooxhMFkDU44K0wCB Z8UiBZUpSTJjbLDsDQEjCjkur1VyJGjxzLN6ODCyjJdx5Ea2rn0au3DcFlqhlfg/s/ny Ddpv0ZQB2n3vCu7jPO2dUQYi7LB0Wl2ybshGBEclZyw3dRMcadG+8PcPmHBQ76PZO9Hf 3w== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t7qj90gdd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 06:56:04 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38K6u3Gc013587 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 06:56:03 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 19 Sep 2023 23:55:54 -0700 From: Tengfei Fan To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , Tengfei Fan Subject: [PATCH v3 4/5] arm64: dts: qcom: add uart console support for SM4450 Date: Wed, 20 Sep 2023 14:54:58 +0800 Message-ID: <20230920065459.12738-5-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230920065459.12738-1-quic_tengfan@quicinc.com> References: <20230920065459.12738-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bjlnyuLNUE96nO3ILyLea7OUJPEtkmGh X-Proofpoint-ORIG-GUID: bjlnyuLNUE96nO3ILyLea7OUJPEtkmGh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_02,2023-09-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 mlxlogscore=878 mlxscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200055 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add base description of UART and TLMM nodes which helps SM4450 boot to shell with console on boards with this SoC. Signed-off-by: Tengfei Fan --- arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++++++++- arch/arm64/boot/dts/qcom/sm4450.dtsi | 50 ++++++++++++++++++++++++- 2 files changed, 65 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts index 00a1c81ca397..0f253a2ba170 100644 --- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts @@ -10,9 +10,23 @@ model = "Qualcomm Technologies, Inc. SM4450 QRD"; compatible = "qcom,sm4450-qrd", "qcom,sm4450"; - aliases { }; + aliases { + serial0 = &uart7; + }; chosen { - bootargs = "console=hvc0"; + stdout-path = "serial0:115200n8"; }; }; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <136 1>; +}; + +&uart7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index c27f17a41699..727d6f7cf220 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -364,6 +364,29 @@ <0>; }; + qupv3_id_0: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + uart7: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; + status = "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -380,6 +403,32 @@ interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sm4450-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 137>; + wakeup-parent = <&pdc>; + + qup_uart7_rx: qup-uart7-rx-state { + pins = "gpio23"; + function = "qup1_se2_l2"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins = "gpio22"; + function = "qup1_se2_l2"; + drive-strength = <2>; + bias-disable; + }; + }; + intc: interrupt-controller@17200000 { compatible = "arm,gic-v3"; reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ @@ -476,7 +525,6 @@ clocks = <&xo_board>; }; }; - }; timer {