From patchwork Thu Sep 14 05:06:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 723314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22A96CA0ECD for ; Thu, 14 Sep 2023 05:07:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232795AbjINFHT (ORCPT ); Thu, 14 Sep 2023 01:07:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233781AbjINFHR (ORCPT ); Thu, 14 Sep 2023 01:07:17 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5331398 for ; Wed, 13 Sep 2023 22:07:13 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2bfc68be09bso4967971fa.1 for ; Wed, 13 Sep 2023 22:07:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694668031; x=1695272831; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=plrluv5QV8EPu2mUJr8YqU8PvbWDvsdMpqG8T+T+sN8=; b=AnSlNSbQ6sYQ5TnDu2gX0L9/m1rbYMHzFDTb86n9dYsvYsdlFhO/avrjsCI4J6aPgu gCAZUpj88YXwTEEbus3CJ9OjPrq8LOYtsa/d+QTWaCeY8jMS6FSTNl/dt6taL81SSW9X yoT7elwi/JBV3wPS39t7/kDvcOYo9OlcknWXffa2rL37Mff7bN5ITlUVajEtI5m64vIm fXsMYrZaBirjT7eh32x4Lh2DGyAUhEdyNFYAcvSQ3yZLBB4V2Ib6IWWkKgxp4eDw3tbS v6oasGQHhy8AmldcUadv6q0Bhp/RCMzGHibKbATl30TGFp73+Pkxv6ho78UauH+QHI1C 6JPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694668031; x=1695272831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=plrluv5QV8EPu2mUJr8YqU8PvbWDvsdMpqG8T+T+sN8=; b=hyBJzaQpPaWDrYR5mnhADHGEYajY8oe7Twt/mFgNg/9lx78rXaPM1/MtAL9pCQKWaC L79R8QVnSGIUPkyGcVTz2Khzw0yv1zgmcZkqNtib0BFKMmw23Fg5C3DFrRqbd2W4foUz nl1EuTCsa/Q50D6LwvRacrqkfuejzrwPe3r+ANBwZun1nw4n9mYklPyGsIUxDx8j2h9d RRxywhBHI1038C9vFb9p+xIxVVHTpV7sZFTLWsA/DXAxLZqAMaGa1i5dA8mVhm3QiACR TggSvG3FrZxzv/l3JpLTPQRnEi1MJaRqREuaC0fCMSm0tNQVRiVKKHe1rWCejseJ5M9y wbiQ== X-Gm-Message-State: AOJu0YzNi40nGjlbi+FLWPI6MT210vnvKkAwbpfgrRgheFH+LBsyGA0o Amhhos0AlsNtiGSsJSSFqAspDg== X-Google-Smtp-Source: AGHT+IHPmITUAbGJTINrlVxZxGUD11N+A3ABBhpQJSR+Sp6EAE1W7ImEI847Ug7zcvatgNaa8bNgsQ== X-Received: by 2002:a2e:a372:0:b0:2bf:af6e:9420 with SMTP id i18-20020a2ea372000000b002bfaf6e9420mr193041ljn.19.1694668031454; Wed, 13 Sep 2023 22:07:11 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id y15-20020a2e978f000000b002bce38190a3sm124777lji.34.2023.09.13.22.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 22:07:11 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v3 05/12] drm/msm/dpu: split dpu_plane_atomic_check() Date: Thu, 14 Sep 2023 08:06:59 +0300 Message-Id: <20230914050706.1058620-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230914050706.1058620-1-dmitry.baryshkov@linaro.org> References: <20230914050706.1058620-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split dpu_plane_atomic_check() function into two pieces: dpu_plane_atomic_check_nopipe() performing generic checks on the pstate, without touching the associated pipe, and dpu_plane_atomic_check_pipes(), which takes into account used pipes. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 178 ++++++++++++++-------- 1 file changed, 112 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 3a75c474c4cd..4b1fbe9dbb3f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -777,46 +777,20 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, return 0; } -static int dpu_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) +static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, + struct drm_plane_state *new_plane_state, + const struct drm_crtc_state *crtc_state) { - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, - plane); - int ret = 0, min_scale; struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe = &pstate->pipe; - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; - const struct drm_crtc_state *crtc_state = NULL; - const struct dpu_format *fmt; struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; struct drm_rect fb_rect = { 0 }; uint32_t max_linewidth; - unsigned int rotation; - uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps; - const struct dpu_sspp_sub_blks *sblk; + int ret = 0; - if (new_plane_state->crtc) - crtc_state = drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); - - pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - r_pipe->sspp = NULL; - - if (!pipe->sspp) - return -EINVAL; - - pipe_hw_caps = pipe->sspp->cap; - sblk = pipe->sspp->cap->sblk; - - min_scale = FRAC_16_16(1, sblk->maxupscale); - ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, - min_scale, - sblk->maxdwnscale << 16, - true, true); + ret = drm_atomic_helper_check_plane_noscale(new_plane_state, crtc_state, + true, true); if (ret) { DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); return ret; @@ -824,11 +798,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (!new_plane_state->visible) return 0; - pipe->multirect_index = DPU_SSPP_RECT_SOLO; - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { DPU_ERROR("> %d plane stages assigned\n", @@ -847,8 +816,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -E2BIG; } - fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); - max_linewidth = pdpu->catalog->caps->max_linewidth; /* state->src is 16.16, src_rect is not */ @@ -861,6 +828,77 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, new_plane_state->rotation); if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + *r_pipe_cfg = *pipe_cfg; + pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; + pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; + r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; + } else { + memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); + } + + drm_rect_rotate_inv(&pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + if (r_pipe_cfg->src_rect.x1 != 0) + drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + + pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); + + return 0; +} + +static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *new_plane_state = + drm_atomic_get_new_plane_state(state, plane); + int ret = 0, min_scale, max_scale; + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + const struct dpu_format *fmt; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; + uint32_t max_linewidth; + unsigned int rotation; + uint32_t supported_rotations; + const struct dpu_sspp_cfg *pipe_hw_caps; + const struct dpu_sspp_sub_blks *sblk; + + pipe_hw_caps = pipe->sspp->cap; + sblk = pipe->sspp->cap->sblk; + + min_scale = FRAC_16_16(1, sblk->maxupscale); + max_scale = sblk->maxdwnscale << 16; + + ret = drm_atomic_helper_check_plane_scale(new_plane_state, min_scale, max_scale); + if (ret) + return ret; + + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); + + max_linewidth = pdpu->catalog->caps->max_linewidth; + + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt); + if (ret) + return ret; + + if (r_pipe_cfg->src_rect.x1 != 0) { /* * In parallel multirect case only the half of the usual width * is supported for tiled formats. If we are here, we know that @@ -873,12 +911,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -E2BIG; } - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } - if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && @@ -900,26 +932,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe->multirect_index = DPU_SSPP_RECT_1; r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - *r_pipe_cfg = *pipe_cfg; - pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; - pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; - r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; - r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; - } - - drm_rect_rotate_inv(&pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - if (r_pipe->sspp) - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - - ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt); - if (ret) - return ret; - - if (r_pipe->sspp) { ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt); if (ret) return ret; @@ -941,11 +953,45 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, } pstate->rotation = rotation; - pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); return 0; } +static int dpu_plane_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); + int ret = 0; + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + const struct drm_crtc_state *crtc_state = NULL; + + if (new_plane_state->crtc) + crtc_state = drm_atomic_get_new_crtc_state(state, + new_plane_state->crtc); + + if (pdpu->pipe != SSPP_NONE) { + pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + r_pipe->sspp = NULL; + } + + if (!pipe->sspp) + return -EINVAL; + + ret = dpu_plane_atomic_check_nopipe(plane, new_plane_state, crtc_state); + if (ret) + return ret; + + if (!new_plane_state->visible) + return 0; + + return dpu_plane_atomic_check_pipes(plane, state); +} + static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) { const struct dpu_format *format =