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[80.115.237.132]) by smtp.gmail.com with ESMTPSA id i15-20020a1709064ecf00b009a2202bfce5sm6957130ejv.118.2023.08.30.02.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 02:58:46 -0700 (PDT) From: Luca Weiss Date: Wed, 30 Aug 2023 11:58:28 +0200 Subject: [PATCH 03/11] arm64: dts: qcom: sc7280: Move qfprom clock to chrome-common MIME-Version: 1.0 Message-Id: <20230830-fp5-initial-v1-3-5a954519bbad@fairphone.com> References: <20230830-fp5-initial-v1-0-5a954519bbad@fairphone.com> In-Reply-To: <20230830-fp5-initial-v1-0-5a954519bbad@fairphone.com> To: cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Linus Walleij , "Rafael J. Wysocki" , Viresh Kumar Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On non-ChromeOS boards the clock cannot be touched, so move it in the chrome-common dtsi which is the only place where it's needed. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 5 +++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 8eb30aa226a2..6cfcec1eabd9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -59,6 +59,11 @@ &pmk8350_pon { status = "disabled"; }; +&qfprom { + clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; + clock-names = "core"; +}; + /* * Chrome designs always boot from SPI flash hooked up to the qspi. * diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 98a8d627a348..5c78038369fd 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -897,8 +897,6 @@ qfprom: efuse@784000 { <0 0x00780000 0 0xa20>, <0 0x00782000 0 0x120>, <0 0x00786000 0 0x1fff>; - clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; - clock-names = "core"; power-domains = <&rpmhpd SC7280_MX>; #address-cells = <1>; #size-cells = <1>;