From patchwork Tue Aug 22 17:42:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 716205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88434EE49AF for ; Tue, 22 Aug 2023 17:42:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229471AbjHVRmz (ORCPT ); Tue, 22 Aug 2023 13:42:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229436AbjHVRmz (ORCPT ); Tue, 22 Aug 2023 13:42:55 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90DBACE9; Tue, 22 Aug 2023 10:42:53 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37MDUxB6006060; Tue, 22 Aug 2023 17:42:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=CE/dOv6xOGZeXktNjhKej/MhIoU0T0WykZkNgHuAtRs=; b=o+VPrsKNDF2egnT9CCSACATdEPrACUo1LMpyK6KIMRPecaJk9efaV3ZYy+qYixQxIOPY ePzlOeU+lh0daV2caEX5x9xEGRqk07ZRob86SM5zWO00I9+qS1jl71w9u/g0IxLkgBbL s4h9qIXax6ptjqgtvQ4d4sefj2wvIULsydriLcPRX3Kfclk0di+WbJxiX/DZ5pHrgoOu zJLOKXn/EQR2qJVL34uLjqsYBiMtGR5WwOmf4qfUoudUMH67lymSyItTplyqE6jbAOmY YMR633Gewu91lL/PZOVtaQa8E80Yqw8H6naC6KxXSsNS2iALwjup6Rn5+Vs4QegwR8P3 0g== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3smasmtsqg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Aug 2023 17:42:47 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37MHgkcY003046 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Aug 2023 17:42:46 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 22 Aug 2023 10:42:45 -0700 From: Jessica Zhang Date: Tue, 22 Aug 2023 10:42:06 -0700 Subject: [PATCH v4 3/4] drm/msm/dsi: Add DATABUS_WIDEN MDP_CTRL2 bit MIME-Version: 1.0 Message-ID: <20230822-add-widebus-support-v4-3-9dc86083d6ea@quicinc.com> References: <20230822-add-widebus-support-v4-0-9dc86083d6ea@quicinc.com> In-Reply-To: <20230822-add-widebus-support-v4-0-9dc86083d6ea@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1692726164; l=984; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=+DwozW2l7XALnMSsnJHlfg5qbfg6fBx2ZBG+vl+XY58=; b=a6N0zcw1OTiTmLIC7T5PtnWosIY34cIPrB9UcQ7+ugpEKd/sg6E6V1gVmQQP46hbennE3GcVo OpOzWXOqrfmC0x8ZUfaP+0SzblLOwo2gNTvmN8015HD8fnuYlkJI84y X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: B1K4gYdqzpwpgFy-99AUBiymYAwAaNsv X-Proofpoint-GUID: B1K4gYdqzpwpgFy-99AUBiymYAwAaNsv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-22_15,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=635 bulkscore=0 clxscore=1015 suspectscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308220140 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a DATABUS_WIDEN bit to the MDP_CTRL2 register to allow DSI to enable databus widen mode. Reviewed-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index a4a154601114..2a7d980e12c3 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -664,6 +664,7 @@ static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap v return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK; } #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000 +#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000 #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f