diff mbox series

[V5,4/8] clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock

Message ID 20230803105741.2292309-5-quic_imrashai@quicinc.com
State Accepted
Commit 06d71fa10f2e507444c6759328a6c19d38eab788
Headers show
Series Update GCC clocks for QDU1000 and QRU1000 SoCs | expand

Commit Message

Imran Shaik Aug. 3, 2023, 10:57 a.m. UTC
gcc_gpll1_out_even clock is referenced as a parent, but not registered
with the clock framework. Hence add support to register the same.

Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
---
Changes since v4:
 - Split the gcc_ddrss_ecpri_gsi_clk clock changes
 - Update the commit text
Changes since v3:
 - None
Changes since v2:
 - Split the patch as per the review comments
 - Newly added

 drivers/clk/qcom/gcc-qdu1000.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 6a6e0f55516a..97fd1947637a 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -2522,6 +2522,7 @@  static struct clk_regmap *gcc_qdu1000_clocks[] = {
 	[GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
 	[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
 	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
+	[GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
 };
 
 static const struct qcom_reset_map gcc_qdu1000_resets[] = {