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[83.9.30.53]) by smtp.gmail.com with ESMTPSA id u9-20020a056512040900b004fe11366146sm2079096lfk.51.2023.07.31.05.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 05:20:16 -0700 (PDT) From: Konrad Dybcio Date: Mon, 31 Jul 2023 14:20:13 +0200 Subject: [PATCH 2/2] clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC MIME-Version: 1.0 Message-Id: <20230731-topic-pcnoc-v1-2-452dd36d11d7@linaro.org> References: <20230731-topic-pcnoc-v1-0-452dd36d11d7@linaro.org> In-Reply-To: <20230731-topic-pcnoc-v1-0-452dd36d11d7@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690806013; l=1116; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=+W0uIDuc/JsKDaPo6r8vR/8nsAtUZyS7FUGMmEfo4sQ=; b=mjwDmDZetZpVGG08tKYROcePohsp0mFSBaoaPmoS+I42e75UwmMpBAtQaRO1wE4gCVsp35qwu +RSHWqkWae7DtQHj3asvZcO0yGj1KBGNZWS3l/6f78yCHljSYvF/9AK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On all supported SoCs to date, the PCNoC (a.k.a CNoC_PERIPH) clock must be always-on as long as the APSS is online and only has to run at 19.2 MHz. Define it to be as such in the ACTIVE domain. Some SoCs use that clock for bus scaling, while others just need it for reaching the hardware. This commit will hurt neither. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-smd-rpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index ebb8d9aac89d..0191fc0dd7da 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -455,7 +455,7 @@ DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_BUS(pcnoc, 0); +DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL); DEFINE_CLK_SMD_RPM_BUS(snoc, 1); DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); DEFINE_CLK_SMD_RPM_BUS(cnoc, 2);