From patchwork Fri Jul 28 17:02:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 707566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32F29C001E0 for ; Fri, 28 Jul 2023 17:03:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235679AbjG1RDd (ORCPT ); Fri, 28 Jul 2023 13:03:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235581AbjG1RDV (ORCPT ); Fri, 28 Jul 2023 13:03:21 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9778526A0; Fri, 28 Jul 2023 10:03:19 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36SDqE38005651; Fri, 28 Jul 2023 17:02:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=0vkReIXSPx/fJ35HjRhaYEwXqFe3+9JCb+YVyZ8Llrg=; b=PjSVYlI/k6mL05lTBNR6+F0xsnEp5grMzjxZTPDU02lyjur4fAWAEdJ/5DUwSluBX/FV 2efc1fKiK2ccCHYAliTdrWfISgRQ5Bib6JmbgxeJFwVzPUmYFWZZn1k7Z4GZkkbpG2QJ jYKp2YeqVxvn1Vf4Wxuo8WPvH8neb1JhMEp+pBHPNYAi2ZRJHYF5RlFL3eXp8mRVNfSb O8evY22b7QsDTFQyBJPqSimRz1DB1b4my226EZtMKGL8YoOLFq4NahlGT0Nk6S2bMOvJ D4GuO0LDGMUe5zZxEAlfa0SdKtTywQdi9syGuFdKIsXFm10Zh0MwW6r/SwinGjuhi4q5 oA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s4ew50fd3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jul 2023 17:02:56 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36SH2trD022302 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jul 2023 17:02:55 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Fri, 28 Jul 2023 10:02:54 -0700 From: Jessica Zhang Date: Fri, 28 Jul 2023 10:02:17 -0700 Subject: [PATCH RFC v5 08/10] drm/msm/dpu: Allow NULL FBs in atomic commit MIME-Version: 1.0 Message-ID: <20230728-solid-fill-v5-8-053dbefa909c@quicinc.com> References: <20230728-solid-fill-v5-0-053dbefa909c@quicinc.com> In-Reply-To: <20230728-solid-fill-v5-0-053dbefa909c@quicinc.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Clark , Dmitry Baryshkov , "Sean Paul" , Marijn Suijten CC: , , , , , , , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-034f2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690563772; l=4407; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=S2zyf9Q7rmRU7w/6ZZvWxtgX0YTYx8yUPaOYRxavcrA=; b=dbh12ajxxu4KcE3gCUhhuMXpdZ/19gejIcsnvPgeXxgMewqkyqPG8nDVf3IgUAp+lum4EOGgz hUocKCcifY9DUhtkcWO6tYaGRvIx87vvOP3qxICpV01IOzCwcbM6Geg X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Dn9XvVGwCo4KwnWjP385E02ovPa08d_8 X-Proofpoint-ORIG-GUID: Dn9XvVGwCo4KwnWjP385E02ovPa08d_8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 malwarescore=0 mlxscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=836 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307280154 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Since solid fill planes allow for a NULL framebuffer in a valid commit, add NULL framebuffer checks to atomic commit calls within DPU. Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 ++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 41 ++++++++++++++++++++----------- 2 files changed, 34 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 1edf2b6b0a26..cff0f0d26b22 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -451,6 +451,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct drm_plane_state *state; struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); struct dpu_plane_state *pstate = NULL; + const struct msm_format *fmt; struct dpu_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; @@ -470,7 +471,13 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, pstate = to_dpu_plane_state(state); fb = state->fb; - format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); + if (drm_plane_solid_fill_enabled(state)) + fmt = dpu_get_msm_format(&_dpu_crtc_get_kms(crtc)->base, + DRM_FORMAT_ABGR8888, 0); + else + fmt = msm_framebuffer_format(pstate->base.fb); + + format = to_dpu_format(fmt); if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index c2aaaded07ed..114c803ff99b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -837,8 +837,13 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, pipe_cfg->dst_rect = new_plane_state->dst; - fb_rect.x2 = new_plane_state->fb->width; - fb_rect.y2 = new_plane_state->fb->height; + if (drm_plane_solid_fill_enabled(new_plane_state)) + return 0; + + if (new_plane_state->pixel_source == DRM_PLANE_PIXEL_SOURCE_FB && new_plane_state->fb) { + fb_rect.x2 = new_plane_state->fb->width; + fb_rect.y2 = new_plane_state->fb->height; + } /* Ensure fb size is supported */ if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || @@ -1082,21 +1087,32 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) struct drm_crtc *crtc = state->crtc; struct drm_framebuffer *fb = state->fb; bool is_rt_pipe; - const struct dpu_format *fmt = - to_dpu_format(msm_framebuffer_format(fb)); + const struct dpu_format *fmt; struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); struct msm_gem_address_space *aspace = kms->base.aspace; struct dpu_hw_fmt_layout layout; bool layout_valid = false; - int ret; - ret = dpu_format_populate_layout(aspace, fb, &layout); - if (ret) - DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - else - layout_valid = true; + if (state->pixel_source == DRM_PLANE_PIXEL_SOURCE_FB && fb) { + int ret; + + fmt = to_dpu_format(msm_framebuffer_format(fb)); + + ret = dpu_format_populate_layout(aspace, fb, &layout); + if (ret) + DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); + else + layout_valid = true; + + DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT + ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), + crtc->base.id, DRM_RECT_ARG(&state->dst), + (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); + } else { + fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); + } pstate->pending = true; @@ -1104,11 +1120,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); pdpu->is_rt_pipe = is_rt_pipe; - DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT - ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), - crtc->base.id, DRM_RECT_ARG(&state->dst), - (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); - dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, drm_mode_vrefresh(&crtc->mode), layout_valid ? &layout : NULL);