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[83.9.1.59]) by smtp.gmail.com with ESMTPSA id y17-20020a197511000000b004fe432108absm326002lfe.182.2023.08.25.08.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Aug 2023 08:38:28 -0700 (PDT) From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:24 +0200 Subject: [PATCH v4 02/10] interconnect: qcom: icc-rpm: Separate out clock rate calulcations MIME-Version: 1.0 Message-Id: <20230726-topic-icc_coeff-v4-2-c04b60caa467@linaro.org> References: <20230726-topic-icc_coeff-v4-0-c04b60caa467@linaro.org> In-Reply-To: <20230726-topic-icc_coeff-v4-0-c04b60caa467@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Michael Turquette , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1692977904; l=2930; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=VC812LO/ioFmOY5nAI+h4fNdcBO7BBenA1HKz6GQWTI=; b=Cc+hIEBSENUCytOdBLVU4wH09thDLSow/mlFKzyEfu4N4vNyEsQNwwwSIZrhuZ6kH7Z4Nov4j I8DUNAoq/XACHguOMYRKKGs1zB30ZkqQlD6p0GiF5zUKt+RqiLNo4Ye X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation for also setting per-node clock rates, separate out the logic that computes it. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpm.c | 53 +++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 8b02aa8aa96a..8c1bfd65d774 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -291,6 +291,32 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, return 0; } +static u64 qcom_icc_calc_rate(struct qcom_icc_provider *qp, struct qcom_icc_node *qn, int ctx) +{ + u64 agg_avg_rate, agg_peak_rate, agg_rate; + + if (qn->channels) + agg_avg_rate = div_u64(qn->sum_avg[ctx], qn->channels); + else + agg_avg_rate = qn->sum_avg[ctx]; + + if (qp->ab_coeff) { + agg_avg_rate = agg_avg_rate * qp->ab_coeff; + agg_avg_rate = div_u64(agg_avg_rate, 100); + } + + if (qp->ib_coeff) { + agg_peak_rate = qn->max_peak[ctx] * 100; + agg_peak_rate = div_u64(qn->max_peak[ctx], qp->ib_coeff); + } else { + agg_peak_rate = qn->max_peak[ctx]; + } + + agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate); + + return div_u64(agg_rate, qn->buswidth); +} + /** * qcom_icc_bus_aggregate - calculate bus clock rates by traversing all nodes * @provider: generic interconnect provider @@ -299,10 +325,9 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_rate) { struct qcom_icc_provider *qp = to_qcom_provider(provider); - u64 agg_avg_rate, agg_peak_rate, agg_rate; struct qcom_icc_node *qn; struct icc_node *node; - int i; + int ctx; /* * Iterate nodes on the provider, aggregate bandwidth requests for @@ -310,27 +335,9 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_r */ list_for_each_entry(node, &provider->nodes, node_list) { qn = node->data; - for (i = 0; i < QCOM_SMD_RPM_STATE_NUM; i++) { - if (qn->channels) - agg_avg_rate = div_u64(qn->sum_avg[i], qn->channels); - else - agg_avg_rate = qn->sum_avg[i]; - - if (qp->ab_coeff) { - agg_avg_rate = agg_avg_rate * qp->ab_coeff; - agg_avg_rate = div_u64(agg_avg_rate, 100); - } - - if (qp->ib_coeff) { - agg_peak_rate = qn->max_peak[i] * 100; - agg_peak_rate = div_u64(qn->max_peak[i], qp->ib_coeff); - } else { - agg_peak_rate = qn->max_peak[i]; - } - - agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate); - - agg_clk_rate[i] = max_t(u64, agg_clk_rate[i], agg_rate); + for (ctx = 0; ctx < QCOM_SMD_RPM_STATE_NUM; ctx++) { + agg_clk_rate[ctx] = max_t(u64, agg_clk_rate[ctx], + qcom_icc_calc_rate(qp, qn, ctx)); } } }