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[83.9.30.53]) by smtp.gmail.com with ESMTPSA id p13-20020a05651238cd00b004fdc7ec5cbesm2016936lft.300.2023.07.31.03.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 03:52:49 -0700 (PDT) From: Konrad Dybcio Date: Mon, 31 Jul 2023 12:52:26 +0200 Subject: [PATCH v2 10/10] clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect MIME-Version: 1.0 Message-Id: <20230726-topic-icc_coeff-v2-10-8c91c6c76076@linaro.org> References: <20230726-topic-icc_coeff-v2-0-8c91c6c76076@linaro.org> In-Reply-To: <20230726-topic-icc_coeff-v2-0-8c91c6c76076@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Michael Turquette , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690800744; l=1713; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=f1Gofilxti3i0Q7jqaHJvi76S1Nc3UXIB2Lux0RrHdA=; b=ZIUV/H1zLb4P75oFYqUV+xIVsQu0TlDVvSL9C1x+GsN0LHv5u4f9SllLH2OqfGr/3ZjJQuUnU BySvUlyDYmXDqr5yX2+veu8TCUSf9we2B7P1Hh2PHBTmHK/Cs2tC7mI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As it turns out, it's yet another interconnect bus clock. Move it there. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-smd-rpm.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 9b5411932594..4a23f6d3eddd 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -567,6 +567,16 @@ static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = { &clk_smd_rpm_bus_2_snoc_clk, }; +static const struct clk_smd_rpm *qcm2290_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_1_cnoc_clk, + &clk_smd_rpm_mmnrt_clk, + &clk_smd_rpm_mmrt_clk, + &clk_smd_rpm_qup_clk, + &clk_smd_rpm_bus_2_snoc_clk, + &clk_smd_rpm_cpuss_gnoc_clk, +}; + static struct clk_smd_rpm *msm8909_clks[] = { [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, @@ -1182,15 +1192,13 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, - [RPM_SMD_CPUSS_GNOC_CLK] = &clk_smd_rpm_cpuss_gnoc_clk, - [RPM_SMD_CPUSS_GNOC_A_CLK] = &clk_smd_rpm_cpuss_gnoc_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { .clks = qcm2290_clks, .num_clks = ARRAY_SIZE(qcm2290_clks), - .icc_clks = sm_qnoc_icc_clks, - .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) + .icc_clks = qcm2290_icc_clks, + .num_icc_clks = ARRAY_SIZE(qcm2290_icc_clks) }; static const struct of_device_id rpm_smd_clk_match_table[] = {