From patchwork Mon Jul 3 17:57:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 698763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39A6BC30654 for ; Mon, 3 Jul 2023 17:58:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230197AbjGCR61 (ORCPT ); Mon, 3 Jul 2023 13:58:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229505AbjGCR60 (ORCPT ); Mon, 3 Jul 2023 13:58:26 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 669F6E60; Mon, 3 Jul 2023 10:58:25 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 363HtlHO003033; Mon, 3 Jul 2023 17:58:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=BTYAeqSWG1uNHEf8QfyNjFJJct+DZt4Z7tIc8EZR4aE=; b=bjUPgpqQ14lsWVpHDhHl1zkv/lwoLwtrVtuyz9FO/i0TAwpsoB+2yDe48mmEKCL8UF/5 cM2QaPmm43c7p2eCVYJsXnybogrkk4GFvvY1K7hHfI+YgtH3ru9ydzv76wGoeGcr2EdC to5Zh0CHziae1jQhr9cGNZ65M/pmxzluR00bDYt65B+VSD5+ExWmN7mIsAVc7mvx1sEh ejl8qS+bLAZOxmLw5k3tUUdKyBCgrjTErnHcEmc0t1YoHaiH1Rno7xTjagEjwHPc1OaN ORmnbEIZm+KOefkwY+gd6t1nYS07w1aKYiU4Dv+po9PdQGTuBboD9Qg7pfxp6AURwZ2f bg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rky5mgmyp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 03 Jul 2023 17:58:18 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 363HwHiq004115 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 3 Jul 2023 17:58:17 GMT Received: from win-platform-upstream01.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.7; Mon, 3 Jul 2023 10:58:12 -0700 From: Sricharan Ramabadhran To: , , , , , , , , , , , , , , , , CC: Subject: [PATCH V2] PCI: qcom: Use PARF_SLV_ADDR_SPACE_SIZE for ops_2_3_3 Date: Mon, 3 Jul 2023 23:27:57 +0530 Message-ID: <20230703175757.2425540-1-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: gMO3IHTtVjSYG44uW62IUS2hk5k67znm X-Proofpoint-GUID: gMO3IHTtVjSYG44uW62IUS2hk5k67znm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-03_13,2023-06-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 spamscore=0 clxscore=1011 mlxscore=0 priorityscore=1501 phishscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307030162 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074 2_3_3 post_init ops. pcie slave addr size was initially set to 0x358, but was wrongly changed to 0x168 as a part of "PCI: qcom: Remove PCIE20_ prefix from register definitions" Fixing it, by using the right macro PARF_SLV_ADDR_SPACE_SIZE and removing the unused PARF_SLV_ADDR_SPACE_SIZE_2_3_3. Without this pcie bring up on IPQ8074 is broken now. Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") Signed-off-by: Sricharan Ramabadhran Reviewed-by: Konrad Dybcio --- [V2] Fixed the 'fixes tag' correctly, subject, right macro usage drivers/pci/controller/dwc/pcie-qcom.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4ab30892f6ef..1689d072fe86 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -43,7 +43,6 @@ #define PARF_PHY_REFCLK 0x4c #define PARF_CONFIG_BITS 0x50 #define PARF_DBI_BASE_ADDR 0x168 -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ #define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 @@ -811,7 +810,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) u32 val; writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN;