From patchwork Wed Aug 23 12:55:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 716169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D76AEE49B0 for ; Wed, 23 Aug 2023 12:56:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235324AbjHWM4S (ORCPT ); Wed, 23 Aug 2023 08:56:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235329AbjHWM4R (ORCPT ); Wed, 23 Aug 2023 08:56:17 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02122E6E for ; Wed, 23 Aug 2023 05:56:08 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-500913779f5so2328038e87.2 for ; Wed, 23 Aug 2023 05:56:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692795366; x=1693400166; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dFC/pTqRgOjYtF1eBy169/e4YScgRvybAMb04hqUx/E=; b=gGcNqCxgXizdrw4zH9jq0MRHZqE9Ff3zvDsJW6BSbaMvyHl+aNCcV60Qhekvml+vct 2Zj7Q2gfxOvhu2yw/e3JZfyAuThtBPmKAFWuhxF3CrNjYkDqSbUzAwnUWohZuHhgMDcY uyX8ZrJo0stiZ/d97Csf7KfSFMCkv0YKkIKw+CFSmkzPz/F8539ouY0L2kVcUmgGO6iR OfRVG9uXl5wtNmghcGJjD2BZioiBOFlZW1mdvNMg3yszSfykr4aiwRQ3OB7vN1Yj6i/I O33OaBh4OwsJuecD42J32IalikISI7Grq8qddEv7i3+bQ+42r78rfIpyvwgBViKVK44m Q9pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692795366; x=1693400166; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dFC/pTqRgOjYtF1eBy169/e4YScgRvybAMb04hqUx/E=; b=GwKvz3UbdUkod37TEMBzHW2CQmj2S65+nWEEmzbydQdwJx9abKec1FjASohixbGUGf NQ7xdg9R3EWMTgaeHNZA6DMIzVL7mdCGHsBvMI5YaNtlUiOeMWUhcWrALREeDYfMXxoK UYv3tNTg5uwjLWUqkQF7f0yovQf8Kooj543XgtMh6Q7oHwjfBF+U0z20SDfT98i7SumB 3GU+I6oLNp55HMU+aSUwKZ3fUZ1ME8zkmO2X3my3j7KDICfrSfAQKoxpt+vuM0nX1aaL BA5aH+Cq/Kt5l0IRfQklaeTwND96Zy2ee4nW/oIWLTJWNkwPIvcMvxH3XrmkwEONGeuQ bHrw== X-Gm-Message-State: AOJu0Yy/2iP72olDxzzQWHy1eIrqtynNaSHzgs9e3bZZqkz0xDNMBPmL oYBEnLa+SKZ/01QKzJ9bUBY87A== X-Google-Smtp-Source: AGHT+IFiMF4+IaX9W1XhNDQgYHgBUlqqxm5khtumufrnr6n+EiF94y1iyY8ZW71sKUhtVa9hXcSQZg== X-Received: by 2002:a2e:4952:0:b0:2b8:39e4:2e2c with SMTP id b18-20020a2e4952000000b002b839e42e2cmr8738640ljd.1.1692795366316; Wed, 23 Aug 2023 05:56:06 -0700 (PDT) Received: from [192.168.1.101] (abyj76.neoplus.adsl.tpnet.pl. [83.9.29.76]) by smtp.gmail.com with ESMTPSA id a18-20020a05651c011200b002b6db0ed72fsm3220256ljb.48.2023.08.23.05.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Aug 2023 05:56:05 -0700 (PDT) From: Konrad Dybcio Date: Wed, 23 Aug 2023 14:55:57 +0200 Subject: [PATCH v3 04/10] drm/msm/a6xx: Add missing regs for A7XX MIME-Version: 1.0 Message-Id: <20230628-topic-a7xx_drmmsm-v3-4-4ee67ccbaf9d@linaro.org> References: <20230628-topic-a7xx_drmmsm-v3-0-4ee67ccbaf9d@linaro.org> In-Reply-To: <20230628-topic-a7xx_drmmsm-v3-0-4ee67ccbaf9d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1692795358; l=2751; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ggC5Dp2QsbNqWJaD+04wUKh0iGm16iYbE0EVpFZJ6dY=; b=px59iQtDNnZvMbWCBOZCRm3tnLVLEQiTyfulSMgFsyJCm6Qxpz6YCRNWcqbeT/QSAxRPKBi2S FvQQTFf93OsBBFrj/kZ7lVdn2iGJrwvzYZmbOk1EATWp9UCW65VXUU9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add some missing definitions required for A7 support. This may be substituted with a mesa header sync. Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 8 ++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 1c051535fd4a..863b5e3b0e67 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1114,6 +1114,12 @@ enum a6xx_tex_type { #define REG_A6XX_CP_MISC_CNTL 0x00000840 #define REG_A6XX_CP_APRIV_CNTL 0x00000844 +#define A6XX_CP_APRIV_CNTL_CDWRITE 0x00000040 +#define A6XX_CP_APRIV_CNTL_CDREAD 0x00000020 +#define A6XX_CP_APRIV_CNTL_RBRPWB 0x00000008 +#define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL 0x00000004 +#define A6XX_CP_APRIV_CNTL_RBFETCH 0x00000002 +#define A6XX_CP_APRIV_CNTL_ICACHE 0x00000001 #define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0 @@ -1939,6 +1945,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f + #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 @@ -8252,5 +8260,6 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 +#define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039 #endif /* A6XX_XML */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index fcd9eb53baf8..5b66efafc901 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -360,6 +360,12 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GMU_GENERAL_7 0x000051cc +#define REG_A6XX_GMU_GENERAL_8 0x000051cd + +#define REG_A6XX_GMU_GENERAL_9 0x000051ce + +#define REG_A6XX_GMU_GENERAL_10 0x000051cf + #define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d #define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920 @@ -471,6 +477,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101 +#define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 0x00000154 + #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180 #define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346