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[83.9.31.165]) by smtp.gmail.com with ESMTPSA id eq21-20020a056512489500b004f4c3feb9fbsm1099235lfb.61.2023.06.22.04.57.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 04:58:00 -0700 (PDT) From: Konrad Dybcio Date: Thu, 22 Jun 2023 13:57:49 +0200 Subject: [PATCH 9/9] arm64: dts: qcom: msm8998: Use the correct GPLL0_DIV leg for MMCC MIME-Version: 1.0 Message-Id: <20230622-topic-8998clk-v1-9-5b7a0d6e98b1@linaro.org> References: <20230622-topic-8998clk-v1-0-5b7a0d6e98b1@linaro.org> In-Reply-To: <20230622-topic-8998clk-v1-0-5b7a0d6e98b1@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jeffrey Hugo , Taniya Das Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687435067; l=1056; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gJtjlM23H/np8JPlgrRMMzMMmFruemZY5INaIEO4+Kg=; b=ZOzGxwxyKdjB5CuoCZtPs1vOWhS12y7dZRhQ3MdXQ/4bwzI2xByM4FWZDx1OQatfW2recggXb 6Hy5kqKivQtDFlZuMQ0ki2sV22O+49Wdan7ocq1Q56hCZGjMNz5OB1y X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MMCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. We've already been using the correct one in the non-div case, start doing so for the other one as well. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 74bd05579796..c4faba092368 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2718,7 +2718,8 @@ mmcc: clock-controller@c8c0000 { "dsi1byte", "hdmipll", "dplink", - "dpvco"; + "dpvco", + "gpll0_div"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, <0>, @@ -2727,7 +2728,8 @@ mmcc: clock-controller@c8c0000 { <0>, <0>, <0>, - <0>; + <0>, + <&gcc GCC_MMSS_GPLL0_DIV_CLK>; }; mmss_smmu: iommu@cd00000 {