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[83.9.31.165]) by smtp.gmail.com with ESMTPSA id eq21-20020a056512489500b004f4c3feb9fbsm1099235lfb.61.2023.06.22.04.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 04:57:49 -0700 (PDT) From: Konrad Dybcio Date: Thu, 22 Jun 2023 13:57:41 +0200 Subject: [PATCH 1/9] dt-bindings: clk: qcom,gcc-msm8998: Add missing GPU/MMSS GPLL0 legs MIME-Version: 1.0 Message-Id: <20230622-topic-8998clk-v1-1-5b7a0d6e98b1@linaro.org> References: <20230622-topic-8998clk-v1-0-5b7a0d6e98b1@linaro.org> In-Reply-To: <20230622-topic-8998clk-v1-0-5b7a0d6e98b1@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jeffrey Hugo , Taniya Das Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687435067; l=894; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=F8sCo+8Xd5XxI+0cPZIVX8PD/zdBEi1oKdosoXzGPrA=; b=A04xy8EGlHpSd10ms85yXgvIRB3fkqXy2CskjHYT7oJEcGjyDh3UOhwLi28idwcWGR5jAsHCa 6mNhZkxGrU+CerQACv/uqDtp1BYXsaK6ozrjnN0/9idcqx71HY2n+iI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GPLL0 has two separate outputs to both GPUSS and MMSS: one that's 2-divided and one that runs at the same rate as the GPLL0 itself. Add the missing ones to the binding. Signed-off-by: Konrad Dybcio --- include/dt-bindings/clock/qcom,gcc-msm8998.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 1badb4f9c58f..b5456a64d421 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -190,6 +190,9 @@ #define AGGRE2_SNOC_NORTH_AXI 181 #define SSC_XO 182 #define SSC_CNOC_AHBS_CLK 183 +#define GCC_MMSS_GPLL0_DIV_CLK 184 +#define GCC_GPU_GPLL0_DIV_CLK 185 +#define GCC_GPU_GPLL0_CLK 186 #define PCIE_0_GDSC 0 #define UFS_GDSC 1