From patchwork Thu Jun 22 23:48:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan McCann X-Patchwork-Id: 694939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABBB4EB64DD for ; Thu, 22 Jun 2023 23:50:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231817AbjFVXun (ORCPT ); Thu, 22 Jun 2023 19:50:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231799AbjFVXui (ORCPT ); Thu, 22 Jun 2023 19:50:38 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5512B2132; Thu, 22 Jun 2023 16:50:33 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35MNivKY030659; Thu, 22 Jun 2023 23:50:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=Jv9N+aS6XZ9yH9zY47Urju/ht5RhYQ5aWXeeHEHYDqY=; b=gGC9jhsyJfX05nU6pZZAgEKdlq/Hn3pswcjI6Zzv4wwt2fUxfaUyZHC2xQgInFpEXcNm UKHbgUsDz1br7Mpp80DwuslxzeMFMUDCPfRQudyueKWnTpbRgus09madltgYZ83Wtndv krJyU+fQEq76aETyBMMBNCuer4IbelyPTpW9+od6owW+D00zX5McHYEXifeIL0i16Nso XXD5kI4kzw4uO85BdC2yFQwLwQRiUJrq5bBcDTSWv9yRqMEqM8zWLFp5xiOFEtr671Hr vjWZJjj/Lf54dQZBMJdYFoKJMmMia+/Hwo6Tu9UGTukO7PTxoqTKg3/Gh5JFHm3ajsvG wQ== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rc6b2bfv7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Jun 2023 23:50:27 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35MNoQwV004713 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Jun 2023 23:50:26 GMT Received: from hu-rmccann-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 22 Jun 2023 16:50:26 -0700 From: Ryan McCann Date: Thu, 22 Jun 2023 16:48:55 -0700 Subject: [PATCH 3/6] drm/msm/dpu: Define names for unnamed sblks MIME-Version: 1.0 Message-ID: <20230622-devcoredump_patch-v1-3-3b2cdcc6a576@quicinc.com> References: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> In-Reply-To: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter CC: Rob Clark , , , , , , Ryan McCann X-Mailer: b4 0.13-dev-8a804 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687477824; l=3066; i=quic_rmccann@quicinc.com; s=20230622; h=from:subject:message-id; bh=lNOMoAT8r4NJwr47/9QKubUDQvUqJC9SfNtvattQY1w=; b=q60r/Cug5vJB9V27Z1tJ4rZLRzWnoDRW5ByBaZpaG9mnSVvJgjbdwBn7CUClo2lbgS4Mly9Tg HRdFq7mNcBqAuzt7IIluFy/cjNcQSfwt3mr95OyaJbhWxXdlw+KYyyu X-Developer-Key: i=quic_rmccann@quicinc.com; a=ed25519; pk=d/uP3OwPGpj/bTtiHvV1RBZ2S6q4AL6j1+A5y+dmbTI= X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hJXBELlhKtNKMhOcO4M_5QAnFGRgGVmP X-Proofpoint-GUID: hJXBELlhKtNKMhOcO4M_5QAnFGRgGVmP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_17,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 spamscore=0 phishscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=919 lowpriorityscore=0 impostorscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some sub blocks in the hw catalog have not been given a name, so when the registers from that block are dumped, there is no name to reference. Define names for relevant sub blocks to fix this. Signed-off-by: Ryan McCann --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 69200b4cf210..8349ecda1f3c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -444,12 +444,12 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { * DSPP sub blocks config *************************************************************/ static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { - .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, + .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x10007}, }; static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { - .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, + .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x40000}, }; @@ -465,19 +465,19 @@ static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { * PINGPONG sub blocks config *************************************************************/ static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { - .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, + .te2 = {.name = "te2", .id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, .version = 0x1}, - .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, + .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, .len = 0x20, .version = 0x10000}, }; static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { - .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, + .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, .len = 0x20, .version = 0x10000}, }; static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { - .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0, + .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0xe0, .len = 0x20, .version = 0x20000}, }; @@ -517,13 +517,13 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { * DSC sub blocks config *************************************************************/ static const struct dpu_dsc_sub_blks dsc_sblk_0 = { - .enc = {.base = 0x100, .len = 0x100}, - .ctl = {.base = 0xF00, .len = 0x10}, + .enc = {.name = "enc", .base = 0x100, .len = 0x100}, + .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, }; static const struct dpu_dsc_sub_blks dsc_sblk_1 = { - .enc = {.base = 0x200, .len = 0x100}, - .ctl = {.base = 0xF80, .len = 0x10}, + .enc = {.name = "enc", .base = 0x200, .len = 0x100}, + .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, }; #define DSC_BLK(_name, _id, _base, _features) \