From patchwork Mon Jun 5 05:29:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sridharan S N X-Patchwork-Id: 690302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08DB8C77B73 for ; Mon, 5 Jun 2023 05:30:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232456AbjFEFaS (ORCPT ); Mon, 5 Jun 2023 01:30:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232785AbjFEFaO (ORCPT ); Mon, 5 Jun 2023 01:30:14 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68DC9DF; Sun, 4 Jun 2023 22:30:12 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3554EGa8006633; Mon, 5 Jun 2023 05:30:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=MpIUIHU9p0eCyZxE78REyRLIjkkdQ+QLg8ky7TutGtM=; b=cE2SSJFti9Wzx4Qz6fww9mOVgeETXPn9jQnS6sTPFTWTxeyoPPd/1MoJPMFGs4kdDimC nk0rrKLWnqATl2jUeso8eAI77zsJBo60EcFGsMDpIw4F8X54xROM+qstYyKe4DSV6nAF od2mWveT7f8+KujjN2SrBCGYNy1N6TuUPzC+BjzuYwm+MlE9fgYD6qENV2Vrzmw/E0lf bDPloFW7dAbJ3DDJJxG8vjGe9MfryuSh89qVIoxiK2MTPj39D4KqldQBBiuLLVQTVKsX 4U0Ui3kfzgURo6MFAbPyjbzBFsbB6Cd4Pu3BjKyb3ASUB5N5j0gn1QnvALC2oSRAJLJX ng== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qyvur2msu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jun 2023 05:30:02 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3555U1pj006431 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 5 Jun 2023 05:30:01 GMT Received: from sridsn-linux.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 4 Jun 2023 22:29:57 -0700 From: Sridharan S N To: , , , , , , , , CC: Sridharan S N Subject: [PATCH V2 1/2] arm64: dts: qcom: ipq5332: enable GPIO based LEDs and Buttons Date: Mon, 5 Jun 2023 10:59:06 +0530 Message-ID: <20230605052907.18837-2-quic_sridsn@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605052907.18837-1-quic_sridsn@quicinc.com> References: <20230605052907.18837-1-quic_sridsn@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: G0tLhAjipc8DY6s1pkJ-q5-ZwXoDp91Q X-Proofpoint-ORIG-GUID: G0tLhAjipc8DY6s1pkJ-q5-ZwXoDp91Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-03_08,2023-06-02_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=877 adultscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 phishscore=0 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306050047 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for wlan-2g LED on GPIO 36 and wps buttons on GPIO 35. Signed-off-by: Sridharan S N --- Changes in V2: - Used the hypen in node name instead of underscore - Dropped the status property arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 42 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts | 42 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 42 +++++++++++++++++++++ 3 files changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts index 3af1d5556950..5bd4ff3ad86b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include +#include #include "ipq5332.dtsi" / { @@ -20,6 +22,32 @@ chosen { stdout-path = "serial0"; }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + led-0 { + gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; }; &blsp1_uart0 { @@ -57,6 +85,20 @@ /* PINCTRL */ &tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + gpio_leds_default: gpio-leds-default-state { + pins = "gpio36"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; function = "blsp1_i2c0"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts index bcf3b31c20e3..36cbebb75c48 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include +#include #include "ipq5332.dtsi" / { @@ -20,6 +22,32 @@ chosen { stdout-path = "serial0"; }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + led-0 { + gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; }; &blsp1_uart0 { @@ -71,6 +99,20 @@ /* PINCTRL */ &tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + gpio_leds_default: gpio-leds-default-state { + pins = "gpio36"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; function = "blsp1_i2c0"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts index 3b6a5cb8bf07..2d27f48f00c0 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include +#include #include "ipq5332.dtsi" / { @@ -20,6 +22,32 @@ chosen { stdout-path = "serial0"; }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + led-0 { + gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; }; &blsp1_uart0 { @@ -64,6 +92,20 @@ /* PINCTRL */ &tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + gpio_leds_default: gpio-leds-default-state { + pins = "gpio36"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio13";