From patchwork Thu Jun 1 16:38:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 689413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74DB3C7EE2F for ; Thu, 1 Jun 2023 16:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231815AbjFAQjV (ORCPT ); Thu, 1 Jun 2023 12:39:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231761AbjFAQjU (ORCPT ); Thu, 1 Jun 2023 12:39:20 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED7C3197 for ; Thu, 1 Jun 2023 09:39:18 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-64fd7723836so754637b3a.1 for ; Thu, 01 Jun 2023 09:39:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685637558; x=1688229558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0Jhi/SGtXf0zcdn3PGnK3djwXYahz8JQorb98x1QvGk=; b=Xn/NRwPDI6HpANyrkks5fzFEE67qAj4af2lWBD1rDIyt1Ney3dCiXRymzDS+XvX4BL H8LoIHenyRU7nik0zxODlsldTuCR4YC1LEUlt3OF5m2I3kuDj4Ck8rUgfdD2JZ+wld0w OhElSzjGv5SjqZ9zi7OBN3ATZaovvPW2ciW5TIGM0Yez9TIUiU1t2AI0VuZ5oQSOGZpW 4WJcNqhFb4C1PHmxBq/dGXNfA+MJ+/T6rcczqUHeyXhPXOXSLAviFY5ryesSFB5JOoJ8 XHNLGQ8uIqLGDE5tRp/i/tJdbo9VpaGLi+oTDDQUwInTG+sGy1Ab0QQy2VCo0gTH+WPd hU2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685637558; x=1688229558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0Jhi/SGtXf0zcdn3PGnK3djwXYahz8JQorb98x1QvGk=; b=SioN0OP5nLhhaLA77XbdfVNdADKh0GxYPlLLyAeHHUXr+T5zp8R75Ee2r6ILKcEb81 p8FFmgkeIOrNbqpzU8qgD67gwoQXLoJHQmXerBV3C36ebMkxO4uNQ6HMa508RMw5grVy w0eA9QqnhJMnq7NCSSa2wQHejRMSmURVVLuntFgz/J3GmkdpLluVY9TwGsIJExEJtW6F ZAF5mXZNTJx3ytZyu1EGc04taq0dtwObrArROREX5F0ySr2x8VE7/Th5jGLFmnTP13Zs wgcN+kJoh1hUKoN+cnK/YUGJBqW/FIxHej+ruomweu14RUnOW8o436yCFrwGsw1fVRSU z+Xg== X-Gm-Message-State: AC+VfDyVYktDl3PeGifK9NAo0JndpD0QjVd5/4J5j0DMyJJxvdUIP7b/ RADHkaA5/KEMTZWLEkjcPTcf X-Google-Smtp-Source: ACHHUZ4c81XxdaW+VFcaYDhF2yAW5EiYmmmxUGAvQerboA7m2X50pNmd0SYbpzZj6NcB4i02zQs2rg== X-Received: by 2002:a05:6a00:15ca:b0:64f:e997:50fc with SMTP id o10-20020a056a0015ca00b0064fe99750fcmr8711274pfu.2.1685637558349; Thu, 01 Jun 2023 09:39:18 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.123]) by smtp.gmail.com with ESMTPSA id a9-20020aa78649000000b0064f83595bbcsm5273630pfo.58.2023.06.01.09.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 09:39:17 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v3 1/8] PCI: qcom: Use DWC helpers for modifying the read-only DBI registers Date: Thu, 1 Jun 2023 22:08:53 +0530 Message-Id: <20230601163900.15500-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> References: <20230601163900.15500-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DWC core already exposes dw_pcie_dbi_ro_wr_{en/dis} helper APIs for enabling and disabling the write access to read only DBI registers. So let's use them instead of doing it manually. Also, the existing code doesn't disable the write access when it's done. This is also fixed now. Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4ab30892f6ef..01795ee7ce45 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -61,7 +61,6 @@ /* DBI registers */ #define AXI_MSTR_RESP_COMP_CTRL0 0x818 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c -#define MISC_CONTROL_1_REG 0x8bc /* MHI registers */ #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 @@ -132,9 +131,6 @@ /* AXI_MSTR_RESP_COMP_CTRL1 register fields */ #define CFG_BRIDGE_SB_INIT BIT(0) -/* MISC_CONTROL_1_REG register fields */ -#define DBI_RO_WR_EN 1 - /* PCI_EXP_SLTCAP register fields */ #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) @@ -826,7 +822,9 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) writel(0, pcie->parf + PARF_Q2A_FLUSH); writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); - writel(DBI_RO_WR_EN, pci->dbi_base + MISC_CONTROL_1_REG); + + dw_pcie_dbi_ro_wr_en(pci); + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); @@ -836,6 +834,8 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); + dw_pcie_dbi_ro_wr_dis(pci); + return 0; }