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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id c25-20020ac24159000000b004cc8196a308sm290902lfi.98.2023.05.30.03.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 03:20:18 -0700 (PDT) From: Konrad Dybcio Date: Tue, 30 May 2023 12:20:10 +0200 Subject: [PATCH 11/20] interconnect: qcom: sdm660: Hook up RPM bus clk definitions MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v1-11-1bf8e6663c4e@linaro.org> References: <20230526-topic-smd_icc-v1-0-1bf8e6663c4e@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v1-0-1bf8e6663c4e@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685442001; l=1925; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=l3PUrbf2IpVVC4OrI1ps60fu75U4WFEl/eEO2eEzYSo=; b=tgIYZox4aB/s0xN4595qERFWi7YVOY0SBoSCRi7Qh7LlAjb6hkXyMYfdynSCD1IJ43FelINFx 20L+j26Kje1CB6XP8U7/y+Ie+5zY7ZqBRQXiN18pP4413H1NL7rORBl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Assign the necessary definitions to migrate to the new bus clock handling mechanism. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/interconnect/qcom/sdm660.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 003fc7d110a7..5743ed680e8e 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -1511,6 +1511,7 @@ static const struct qcom_icc_desc sdm660_a2noc = { .type = QCOM_ICC_NOC, .nodes = sdm660_a2noc_nodes, .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes), + .bus_clk_desc = &aggre2_clk, .intf_clocks = a2noc_intf_clocks, .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks), .regmap_cfg = &sdm660_a2noc_regmap_config, @@ -1539,6 +1540,7 @@ static const struct qcom_icc_desc sdm660_bimc = { .type = QCOM_ICC_BIMC, .nodes = sdm660_bimc_nodes, .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), + .bus_clk_desc = &bimc_clk, .regmap_cfg = &sdm660_bimc_regmap_config, }; @@ -1593,6 +1595,7 @@ static const struct qcom_icc_desc sdm660_cnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_cnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes), + .bus_clk_desc = &bus_2_clk, .regmap_cfg = &sdm660_cnoc_regmap_config, }; @@ -1655,6 +1658,7 @@ static const struct qcom_icc_desc sdm660_mnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_mnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), + .bus_clk_desc = &mmaxi_0_clk, .intf_clocks = mm_intf_clocks, .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), .regmap_cfg = &sdm660_mnoc_regmap_config, @@ -1692,6 +1696,7 @@ static const struct qcom_icc_desc sdm660_snoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_snoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes), + .bus_clk_desc = &bus_1_clk, .regmap_cfg = &sdm660_snoc_regmap_config, };