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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id x27-20020ac25ddb000000b004f37a64c90asm785823lfq.303.2023.05.15.06.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 May 2023 06:04:28 -0700 (PDT) From: Konrad Dybcio Date: Mon, 15 May 2023 15:04:13 +0200 Subject: [PATCH 2/5] arm64: dts: qcom: qrb4210-rb2: Enable display out MIME-Version: 1.0 Message-Id: <20230515-topic-rb2-bits-v1-2-a52d154a639d@linaro.org> References: <20230515-topic-rb2-bits-v1-0-a52d154a639d@linaro.org> In-Reply-To: <20230515-topic-rb2-bits-v1-0-a52d154a639d@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bhupesh Sharma Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684155864; l=2637; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=avvssNTgG0e3S5Kryg79ULmCxgvbqADEkl/jEuLJ6M4=; b=weZU+7DXgUJ9tQ8ae/JaYWlwn62DzmanmUnc1lZooL601zypgm81gQOp3Eulc7oCgnUg4JLEi N41WnNPI7+BAJ5s6NQg3AUTPqXrgGBTJhaxDoeaXiX9Q0GVGjG3cJew X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The RB2 has a HDMI output via an LT9611UXC bridge. Set it up. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 88 +++++++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 80c6b59c8ff6..9b539720f05d 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -19,6 +19,17 @@ chosen { stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { compatible = "regulator-fixed"; regulator-name = "VREG_HDMI_OUT_1P2"; @@ -109,6 +120,68 @@ &eud { status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_hdmi_out_1p2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l18a_1p232>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -312,11 +385,24 @@ &sleep_clk { }; &tlmm { - gpio-reserved-ranges = <37 5>, <43 2>, <47 1>, + gpio-reserved-ranges = <43 2>, <47 1>, <49 1>, <52 1>, <54 1>, <56 3>, <61 2>, <64 1>, <68 1>, <72 8>, <96 1>; + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio41"; + function = "gpio"; + input-disable; + output-high; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio46"; + function = "gpio"; + bias-disable; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio88"; function = "gpio";