Message ID | 20230422000839.1921358-3-dmitry.baryshkov@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | drm/msm/dpu: drop _sspp_subblk_offset() | expand |
On 4/21/2023 5:08 PM, Dmitry Baryshkov wrote: > Stop using _sspp_subblk_offset() to get offset of the scaler_blk. Inline > this function and use ctx->cap->sblk->scaler_blk.base directly. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 27 +++++++-------------- > 1 file changed, 9 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c > index fce135f010d4..22c59f2250be 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c > @@ -149,11 +149,6 @@ static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx, > sblk = ctx->cap->sblk; > > switch (s_id) { > - case DPU_SSPP_SCALER_QSEED2: > - case DPU_SSPP_SCALER_QSEED3: > - case DPU_SSPP_SCALER_RGB: > - *idx = sblk->scaler_blk.base; > - break; > case DPU_SSPP_CSC: > case DPU_SSPP_CSC_10BIT: > *idx = sblk->csc_blk.base; > @@ -195,22 +190,21 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) > static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, > u32 mask, u8 en) > { > - u32 idx; > + const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk; > u32 opmode; > > if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) || > - _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || > !test_bit(DPU_SSPP_CSC, &ctx->cap->features)) > return; > > - opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); > + opmode = DPU_REG_READ(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE); > > if (en) > opmode |= mask; > else > opmode &= ~mask; > > - DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); > + DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode); > } > > static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, > @@ -416,25 +410,22 @@ static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, > struct dpu_hw_scaler3_cfg *scaler3_cfg, > const struct dpu_format *format) > { > - u32 idx; > - > - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) > - || !scaler3_cfg) > + if (!ctx || !scaler3_cfg) > return; > > - dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, > + dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, > + ctx->cap->sblk->scaler_blk.base, > ctx->cap->sblk->scaler_blk.version, > format); > } > > static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) > { > - u32 idx; > - > - if (!ctx || _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)) > + if (!ctx) > return 0; > > - return dpu_hw_get_scaler3_ver(&ctx->hw, idx); > + return dpu_hw_get_scaler3_ver(&ctx->hw, > + ctx->cap->sblk->scaler_blk.base); > } > > /* Reviewed-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index fce135f010d4..22c59f2250be 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -149,11 +149,6 @@ static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx, sblk = ctx->cap->sblk; switch (s_id) { - case DPU_SSPP_SCALER_QSEED2: - case DPU_SSPP_SCALER_QSEED3: - case DPU_SSPP_SCALER_RGB: - *idx = sblk->scaler_blk.base; - break; case DPU_SSPP_CSC: case DPU_SSPP_CSC_10BIT: *idx = sblk->csc_blk.base; @@ -195,22 +190,21 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { - u32 idx; + const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk; u32 opmode; if (!test_bit(DPU_SSPP_SCALER_QSEED2, &ctx->cap->features) || - _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || !test_bit(DPU_SSPP_CSC, &ctx->cap->features)) return; - opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); + opmode = DPU_REG_READ(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE); if (en) opmode |= mask; else opmode &= ~mask; - DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); + DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode); } static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, @@ -416,25 +410,22 @@ static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, struct dpu_hw_scaler3_cfg *scaler3_cfg, const struct dpu_format *format) { - u32 idx; - - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) - || !scaler3_cfg) + if (!ctx || !scaler3_cfg) return; - dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, + dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, + ctx->cap->sblk->scaler_blk.base, ctx->cap->sblk->scaler_blk.version, format); } static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) { - u32 idx; - - if (!ctx || _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)) + if (!ctx) return 0; - return dpu_hw_get_scaler3_ver(&ctx->hw, idx); + return dpu_hw_get_scaler3_ver(&ctx->hw, + ctx->cap->sblk->scaler_blk.base); } /*
Stop using _sspp_subblk_offset() to get offset of the scaler_blk. Inline this function and use ctx->cap->sblk->scaler_blk.base directly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 27 +++++++-------------- 1 file changed, 9 insertions(+), 18 deletions(-)