Message ID | 20230411-dpu-intf-te-v2-7-ef76c877eb97@somainline.org |
---|---|
State | Superseded |
Headers | show |
Series | drm/msm/dpu: Implement tearcheck support on INTF block | expand |
On 17.04.2023 22:21, Marijn Suijten wrote: > A bunch of registers were appended at the end in e.g. 91143873a05d > ("drm/msm/dpu: Add MISR register support for interface") rather than > being inserted in a place that maintains numerical sorting. Restore > that. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index 1d22d7dc99b8..1491568f86fc 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -36,6 +36,10 @@ > #define INTF_CONFIG2 0x060 > #define INTF_DISPLAY_DATA_HCTL 0x064 > #define INTF_ACTIVE_DATA_HCTL 0x068 > + > +#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 > +#define INTF_PANEL_FORMAT 0x090 > + > #define INTF_FRAME_LINE_COUNT_EN 0x0A8 > #define INTF_FRAME_COUNT 0x0AC > #define INTF_LINE_COUNT 0x0B0 > @@ -44,8 +48,6 @@ > #define INTF_DEFLICKER_STRNG_COEFF 0x0F4 > #define INTF_DEFLICKER_WEAK_COEFF 0x0F8 > > -#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 > -#define INTF_PANEL_FORMAT 0x090 > #define INTF_TPG_ENABLE 0x100 > #define INTF_TPG_MAIN_CONTROL 0x104 > #define INTF_TPG_VIDEO_CONFIG 0x108 > @@ -57,6 +59,9 @@ > #define INTF_PROG_FETCH_START 0x170 > #define INTF_PROG_ROT_START 0x174 > > +#define INTF_MISR_CTRL 0x180 > +#define INTF_MISR_SIGNATURE 0x184 > + > #define INTF_MUX 0x25C > #define INTF_STATUS 0x26C > > @@ -66,9 +71,6 @@ > #define INTF_CFG2_DATABUS_WIDEN BIT(0) > #define INTF_CFG2_DATA_HCTL_EN BIT(4) > > -#define INTF_MISR_CTRL 0x180 > -#define INTF_MISR_SIGNATURE 0x184 > - > static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, > const struct dpu_mdss_cfg *m, > void __iomem *addr, >
On 2023-04-20 03:47:57, Dmitry Baryshkov wrote: > On 17/04/2023 23:21, Marijn Suijten wrote: > > A bunch of registers were appended at the end in e.g. 91143873a05d > > ("drm/msm/dpu: Add MISR register support for interface") rather than > > being inserted in a place that maintains numerical sorting. Restore > > that. > > Assuming that = "sort order": This is what I mean(t) to say, but not what I meant to write. See the previous sentence: "restore that" refers to "numerical sorting" (not just "sort order") right before. > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > If I don't forget, I'll fix it when applying. If you feel the above explanation is inadequate, feel free to replace the sentence with "Restore said numerical sorting". - Marijn > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 +++++++----- > > 1 file changed, 7 insertions(+), 5 deletions(-) > > > > -- > With best wishes > Dmitry >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 1d22d7dc99b8..1491568f86fc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -36,6 +36,10 @@ #define INTF_CONFIG2 0x060 #define INTF_DISPLAY_DATA_HCTL 0x064 #define INTF_ACTIVE_DATA_HCTL 0x068 + +#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 +#define INTF_PANEL_FORMAT 0x090 + #define INTF_FRAME_LINE_COUNT_EN 0x0A8 #define INTF_FRAME_COUNT 0x0AC #define INTF_LINE_COUNT 0x0B0 @@ -44,8 +48,6 @@ #define INTF_DEFLICKER_STRNG_COEFF 0x0F4 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8 -#define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084 -#define INTF_PANEL_FORMAT 0x090 #define INTF_TPG_ENABLE 0x100 #define INTF_TPG_MAIN_CONTROL 0x104 #define INTF_TPG_VIDEO_CONFIG 0x108 @@ -57,6 +59,9 @@ #define INTF_PROG_FETCH_START 0x170 #define INTF_PROG_ROT_START 0x174 +#define INTF_MISR_CTRL 0x180 +#define INTF_MISR_SIGNATURE 0x184 + #define INTF_MUX 0x25C #define INTF_STATUS 0x26C @@ -66,9 +71,6 @@ #define INTF_CFG2_DATABUS_WIDEN BIT(0) #define INTF_CFG2_DATA_HCTL_EN BIT(4) -#define INTF_MISR_CTRL 0x180 -#define INTF_MISR_SIGNATURE 0x184 - static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, const struct dpu_mdss_cfg *m, void __iomem *addr,
A bunch of registers were appended at the end in e.g. 91143873a05d ("drm/msm/dpu: Add MISR register support for interface") rather than being inserted in a place that maintains numerical sorting. Restore that. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)