From patchwork Thu Apr 6 20:07:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 671599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04476C77B6F for ; Thu, 6 Apr 2023 20:07:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238238AbjDFUHy (ORCPT ); Thu, 6 Apr 2023 16:07:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238598AbjDFUHx (ORCPT ); Thu, 6 Apr 2023 16:07:53 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 710398A51 for ; Thu, 6 Apr 2023 13:07:51 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id j1so1330850wrb.0 for ; Thu, 06 Apr 2023 13:07:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1680811670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J5KzQ/setbKY8lyetTIrWZS3cTz0x9uOqzpCXoBBYus=; b=OO7jftT3SEXL7Jt/pRI20vYdPY/73+/0XyoXNvxBoPfyoll4Yyr+Gw/r1FoyWnGyrd QvC9lBn7bfzuj8Fd4A8gbxtUPMQj4JoTXHC4ZEmeOSv5UdmFvw2x8xFuSLnHjcpRQ3Ir XTaHCtLJpZxIU26TuSNmWrb+b00AwpH6w4YgY2t4l2GUd2kpnweSUkXe03MOVpyeYrf8 depcmgn2NLToadIh74sw9eJhMCMLzTHUJdLtVgjFowqzfUvDwLLb+49mhGKewQElijla UjCONa4S8sZ8I1ezXcrVX2ajQrRNFKTbCXZ1111h1OZ0Rfaqs9LgbT2GO9ZENdrvRYA9 5dCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680811670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J5KzQ/setbKY8lyetTIrWZS3cTz0x9uOqzpCXoBBYus=; b=MyuuSk8phlNbORNGnebjQ5bEtfveBZvfKT5zFOYFLCNziVu+4IenywSrtGvQB9xxGS WQqufNhKi/n+m8PQzrjFdvBX7p1Fv4bqFjOgUSc41I04i7oWvvZyY7fmpcYDvGHM+CG1 vPYda45jhlBetYC1hxqrdBNAQouBpCtN33Anr8I+mznu42sEa9jtjEdSmHnGlHUUCHKY yqvI/8wOYEXufy+gWVSzTYqZeUMnLBd+dFN3b+GF6zRlmW3g8wU4N8QX9HXcVwxgNtIm pmjHz54im5p5aHYbLD2rdHtkg9/FJnxTpUmZEWUsM5OhKuvtkJdXg1lh+5UYentEngP4 CTHg== X-Gm-Message-State: AAQBX9eL2czgi0i8XBiYt00z77EUYreya39PW5ogE+KQj2Eyb8THKR7B bxPQkEdQupR/EthXssmjgVQRuA== X-Google-Smtp-Source: AKy350azZmS1Sul6NSqnkoda4N2fOk9MomlerAJ20oYikPJzyB/PwBlu093sjvClP2uDUvvH/AARwQ== X-Received: by 2002:adf:f1c8:0:b0:2c3:e7d8:245c with SMTP id z8-20020adff1c8000000b002c3e7d8245cmr6907217wro.13.1680811669938; Thu, 06 Apr 2023 13:07:49 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:4793:cb9a:340b:2f72]) by smtp.gmail.com with ESMTPSA id c11-20020adfe74b000000b002d89e113691sm2560506wrn.52.2023.04.06.13.07.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 13:07:49 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski , Krzysztof Kozlowski Subject: [PATCH v2 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Date: Thu, 6 Apr 2023 22:07:17 +0200 Message-Id: <20230406200723.552644-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230406200723.552644-1-brgl@bgdev.pl> References: <20230406200723.552644-1-brgl@bgdev.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bartosz Golaszewski Add the compatible for the Qualcomm Graphics Clock control module present on sa8775p platforms. It matches the generic QCom GPUCC description. Add device-specific DT bindings defines as well. Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski Acked-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + .../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 +++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index db53eb288995..1e3dc9deded9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -15,6 +15,7 @@ description: | See also:: include/dt-bindings/clock/qcom,gpucc-sdm845.h + include/dt-bindings/clock/qcom,gpucc-sa8775p.h include/dt-bindings/clock/qcom,gpucc-sc7180.h include/dt-bindings/clock/qcom,gpucc-sc7280.h include/dt-bindings/clock/qcom,gpucc-sc8280xp.h @@ -27,6 +28,7 @@ properties: compatible: enum: - qcom,sdm845-gpucc + - qcom,sa8775p-gpucc - qcom,sc7180-gpucc - qcom,sc7280-gpucc - qcom,sc8180x-gpucc diff --git a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h new file mode 100644 index 000000000000..a5fd784b1ea2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CX_SNOC_DVM_CLK 7 +#define GPU_CC_CXO_AON_CLK 8 +#define GPU_CC_CXO_CLK 9 +#define GPU_CC_DEMET_CLK 10 +#define GPU_CC_DEMET_DIV_CLK_SRC 11 +#define GPU_CC_FF_CLK_SRC 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 15 +#define GPU_CC_HUB_AON_CLK 16 +#define GPU_CC_HUB_CLK_SRC 17 +#define GPU_CC_HUB_CX_INT_CLK 18 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 19 +#define GPU_CC_MEMNOC_GFX_CLK 20 +#define GPU_CC_SLEEP_CLK 21 +#define GPU_CC_XO_CLK_SRC 22 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_FF_BCR 4 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 +#define GPUCC_GPU_CC_GMU_BCR 6 +#define GPUCC_GPU_CC_GX_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +#endif /* _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H */