From patchwork Fri May 5 21:23:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 679390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD9A4C77B7F for ; Fri, 5 May 2023 21:24:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232809AbjEEVYN (ORCPT ); Fri, 5 May 2023 17:24:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232813AbjEEVYM (ORCPT ); Fri, 5 May 2023 17:24:12 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 874B01BC; Fri, 5 May 2023 14:24:11 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 345KRkNU002609; Fri, 5 May 2023 21:24:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=ONl2dre1X+5P9EF/VMp0fOJtCsY8r5izN5dRFCbZLxE=; b=BdDG+0ycxjLry15UFVDYuyqAz7RtZVbg42nvSi+7h1mMvv1FxTZLTOjkZRRg2Ed2bQEb hlLUd5s7pBMYhx0iewZKiGhsuOJ4OMZlZwfNGYxf5Bv0Rfhb5LKkR1M7JDGbTGKnwkub hE5esTDG5CfnINlV4xetjzzo4uVgOOTVd+xK+YDSLSDyJHRIX1WEwlbwe759kGTRJmMv wSk6u4l34uPFwcFpfb2iTSkrsjYqQIkNvgm/AjIffzdUirBfxauq7eqDA0VxMyexyBRa 2o9t7359VwExSuPk9ww2VpqKTm32N/vOoiJ6n5l5/ed7QY1SCoefT95SlBWLgKFmLPru pA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qd8ud03ay-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 05 May 2023 21:24:05 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 345LO4sL004035 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 5 May 2023 21:24:04 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 5 May 2023 14:24:04 -0700 From: Jessica Zhang Date: Fri, 5 May 2023 14:23:50 -0700 Subject: [PATCH v2 3/4] drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag MIME-Version: 1.0 Message-ID: <20230405-add-dsc-support-v2-3-1072c70e9786@quicinc.com> References: <20230405-add-dsc-support-v2-0-1072c70e9786@quicinc.com> In-Reply-To: <20230405-add-dsc-support-v2-0-1072c70e9786@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten CC: Konrad Dybcio , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683321843; l=2061; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=oOPr2EYXRbZzS1nJp0nk1lw2BUUUgaLElUYeZTpTcg0=; b=5rDXC25jJIq6Zb0Z7v7vIPquLDVz6SJOjrBos5q2yq6jDcE/eWjJwf/qm5RQcFhmDlNIY9wiI udgFmWfmYN1CkWUlq4Yz23NPo7rLRN2aD6W4hWZRQvW4lmEEvsdmUO0 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: o7schd_PYhIoItvvciSKPFHIWHQ1pFek X-Proofpoint-GUID: o7schd_PYhIoItvvciSKPFHIWHQ1pFek X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-05_27,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 adultscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=612 clxscore=1015 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305050173 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DATA_COMPRESS feature flag to DPU INTF block. In DPU 7.x and later, DSC/DCE enablement registers have been moved from PINGPONG to INTF. As core_rev (and related macros) was removed from the dpu_kms struct, the most straightforward way to indicate the presence of this register would be to have a feature flag. Changes in v2: - Changed has_data_compress dpu_cap to a DATA_COMPRESS INTF feature flag Signed-off-by: Jessica Zhang Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 7944481d0a33..c74051906d05 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -104,7 +104,7 @@ #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED)) -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) +#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_DATA_COMPRESS) #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4eda2cc847ef..01c65f940f2a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -185,6 +185,7 @@ enum { * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register + * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register * @DPU_INTF_MAX */ enum { @@ -192,6 +193,7 @@ enum { DPU_INTF_TE, DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, + DPU_INTF_DATA_COMPRESS, DPU_INTF_MAX };